Automated Double Patterning Loop Violation Resolution
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Solution Overview
Problem
Double patterning loop violations in IC design layouts pose challenges due to constraints in photolithographic processes, making it difficult to increase feature density beyond certain thresholds, and existing solutions like manual editing and Rip and Reroute techniques are inefficient and computation-intensive.
Innovation Solution
A method is developed to automatically generate and prioritize design solutions that resolve double patterning loop violations by identifying pairs of edges, computing costs for potential movements, and selecting solutions that minimize new design rule violations, or by decomposing shapes using splicing graphs to break the loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual editing or Rip and Reroute techniques are used to resolve double patterning loop violations, then the violations can be fixed, but the process becomes time-consuming and computation-intensive
Solution Approach 1:
The system automatically resolves double patterning loop violations without requiring manual intervention. The automated loop violation resolver analyzes the design layout, identifies loop violations, and applies fixes autonomously, allowing the system to serve itself rather than requiring human editors to manually resolve each violation through time-consuming iterative processes
Solution Approach 2:
The patent replaces manual mechanical editing processes with an automated computational system. Instead of requiring designers to manually edit layouts or use computation-intensive Rip and Reroute techniques, the system uses algorithmic analysis and automated rule application to resolve violations efficiently, substituting human computational effort with automated digital processing
2Reliability
If existing solutions like Rip and Reroute are applied to fix violations, then design rule violations are resolved, but many new design rule violations are introduced
Solution Approach 1:
The system performs preliminary analysis of the design layout to identify all potential loop violations before applying fixes. By pre-analyzing the complete set of constraints and using this information to guide the resolution process, the system can apply fixes that resolve current violations while preserving other design rules, rather than introducing new violations as happens with reactive Rip and Reroute approaches
Solution Approach 2:
The automated resolver uses feedback from design rule checking to guide its fix application. The system continuously validates proposed solutions against design rules and adjusts its approach based on the impact analysis, ensuring that fixes resolve loop violations without creating new violations, unlike blind Rip and Reroute methods that ignore broader contextual constraints
3Ease of manufacture
If photolithographic process constraints are used to limit feature size, then manufacturing feasibility is maintained, but feature density cannot be increased beyond certain thresholds
Solution Approach 1:
The patent segments the design layout into different regions and applies different coloring strategies to various portions of the layout. By dividing the complete layout into multiple sub-regions that can be independently optimized and colored, the system can achieve higher overall feature density while maintaining manufacturability in each segment, rather than being constrained by a single uniform coloring approach
Data Source
AI summary
A method for automatically generating and prioritizing several design solutions that resolve a double patterning (DP) loop violation in an IC design layout. The method of some embodiments receives a DP loop violation marker and identifies pairs of edges of shapes that form a double patterning loop based on the DP loop violation marker. For each pair of edges that violates the design rule, the method generates one or more design solutions. Each design solution moves a single edge or both edges to resolve the violation. The method of some embodiments computes the cost of applying each design solution to the IC design layout and prioritizes the generated solutions for all the identified pairs of edges based on the computed cost for each solution. The method in some embodiments then selects a solution from the prioritized solutions and applies the selected solution to the design layout.