DPD LUT Switching for Power Amplifier Nonlinearity Compensation
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Solution Overview
Problem
Digital pre-distortion (DPD) techniques face challenges in efficiently compensating for the non-linearity of power amplifier (PA) circuitry in wireless communication systems, particularly at higher signal bandwidths, leading to increased harmonic distortion and inter-modulation spectral components, which affect adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM), thereby reducing signal decoding probability.
Innovation Solution
The implementation of a digital pre-distortion correction method using a generalized memory polynomial (GMP) model with parallelized digital circuitry and lookup tables (LUTs), along with dynamic deviation reduction (DDR) models, to accurately model and compensate for PA non-linearity, reducing area and power consumption, and improving pre-distortion modeling accuracy at higher bandwidths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If digital pre-distortion techniques are used to compensate for power amplifier non-linearity, then signal quality improves, but device complexity and power consumption increase
Solution Approach 1:
The patent segments the DPD computation into multiple parallel processing paths, each handling specific polynomial terms. The generalized memory polynomial model is divided into separate calculation branches that can be independently implemented, reducing the complexity of any single processing unit while maintaining overall accuracy.
Solution Approach 2:
The patent implements dynamic computation by conditionally evaluating polynomial terms based on signal characteristics. The system adapts the complexity of DPD processing in real-time, activating only necessary computational paths depending on operating conditions, thus reducing average device complexity and power consumption.
2Reliability
If digital pre-distortion techniques are used to compensate for power amplifier non-linearity, then signal quality improves, but power consumption increases
Solution Approach 1:
The patent implements partial DPD computation by selectively evaluating only the necessary polynomial terms based on signal conditions. Rather than always computing the full generalized memory polynomial model, the system performs partial computations when full compensation is not required, reducing power consumption while maintaining adequate signal quality.
Solution Approach 2:
The system dynamically adjusts computational effort based on operating conditions, signal bandwidth, and power requirements. The DPD processor adapts its complexity in real-time, reducing power consumption during low-demand periods while maintaining high signal quality when needed.
3Productivity
If higher signal bandwidths are used, then communication capacity increases, but harmonic distortion and inter-modulation spectral components increase
Solution Approach 1:
The patent applies pre-distortion computation before power amplification to pre-compensate for non-linear effects. By calculating the inverse of the expected distortion and applying it in advance through the generalized memory polynomial model, the system prevents harmonic distortion and inter-modulation components from occurring, enabling higher bandwidth operation without increased distortion.
4Device complexity
If traditional DPD models are used, then implementation is simpler, but modeling accuracy at higher bandwidths deteriorates
Solution Approach 1:
The patent transitions from traditional DPD models to the generalized memory polynomial model, changing the mathematical parameters and structure of the distortion compensation. This parameter change introduces memory effects and higher-order terms that accurately capture non-linear behavior at higher bandwidths, improving modeling accuracy despite increased implementation complexity.
Data Source
AI summary
An example method includes switching a first multiplexer circuit associated with first delay circuitry from (a) a first sub-lookup table (LUT) of a first LUT of digital pre-distortion (DPD) corrector circuitry to (b) a first corresponding sub-LUT of a second LUT of the DPD corrector circuitry, the first sub-LUT associated with the first delay circuitry, the second LUT storing updated values to compensate for non-linearity of power amplifier circuitry of a transmitter including the DPD corrector circuitry. The method includes, based on a value of a counter being equal to a difference between (1) a first delay of the first delay circuitry and (2) a second delay of second delay circuitry, switching a second multiplexer circuit associated with the second delay circuitry from (a) a second sub-LUT of the first LUT to (b) a second corresponding sub-LUT of the second LUT, the second sub-LUT associated with the second delay circuitry.