Digital Predistortion Sampling-Rate Shift for Lower DAC Oversampling

Solution Overview

Problem

Digital predistortion (DPD) in wireless communications systems requires high sampling rates for DAC and ADC converters, leading to increased power consumption and complexity due to the need for oversampled signals, which is inefficient and costly.

Innovation Solution

Implementing reduced output sampling rate DPD devices that convert signals to a lower sampling rate after predistortion, allowing DAC and ADC to operate closer to the baseband signal bandwidth, thereby reducing power consumption and complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high sampling rates are used for DAC and ADC converters in DPD, then distortion correction effectiveness is improved, but power consumption and device complexity increase

Engineering Contradiction:

Improvedistortion correction effectivenessVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the sampling rate requirement into two distinct stages: a high sampling rate during the predistortion processing stage to ensure distortion correction effectiveness, and a reduced sampling rate during the DAC conversion stage to reduce power consumption. This segmentation allows each stage to operate at the minimum necessary sampling rate for its specific function, resolving the contradiction between effectiveness and power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the sampling rate parameter dynamically across different processing stages. The sampling rate is set to a first value (higher) during predistortion signal generation and then changed to a second value (lower) during DAC conversion. This parameter change enables the system to maintain distortion correction effectiveness where needed while reducing power consumption where high sampling rates are not critical.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If high sampling rates are used for DAC and ADC converters in DPD, then distortion correction effectiveness is improved, but device complexity increases

Engineering Contradiction:

Improvedistortion correction effectivenessVSAvoidconverter complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the sampling rate requirement into two distinct stages: a high sampling rate during the predistortion processing stage to ensure distortion correction effectiveness, and a reduced sampling rate during the DAC conversion stage to reduce power consumption. This segmentation allows each stage to operate at the minimum necessary sampling rate for its specific function, resolving the contradiction between effectiveness and power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the sampling rate parameter dynamically across different processing stages. The sampling rate is set to a first value (higher) during predistortion signal generation and then changed to a second value (lower) during DAC conversion. This parameter change enables the system to maintain distortion correction effectiveness where needed while reducing power consumption where high sampling rates are not critical.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If oversampled signals are used in DPD, then distortion correction effectiveness is improved, but power consumption increases

Engineering Contradiction:

Improvedistortion correction effectivenessVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies partial oversampling - using a higher sampling rate than the minimum Nyquist rate during the predistortion processing stage to ensure effective distortion correction, but then reducing the sampling rate before DAC conversion. This partial application of oversampling provides the necessary margin for effective DPD while avoiding the excessive power consumption that would result from maintaining high sampling rates throughout the entire signal path.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the sampling rate parameter dynamically across different processing stages. The sampling rate is set to a first value (higher) during predistortion signal generation and then changed to a second value (lower) during DAC conversion. This parameter change enables the system to maintain distortion correction effectiveness where needed while reducing power consumption where high sampling rates are not critical.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10541657B2Method and apparatus for digital pre-distortion with reduced oversampling output ratio

Publication Date: 2020.01.21 QUALCOMM INC

AI summary

Certain aspects of the present disclosure are directed to a digital predistortion (DPD) device for use within a wireless transmitter that permits the use of a downstream digital-to-analog converter that operates at a clock rate close to the bandwidth of a digital baseband input signal. In some examples, a sampling rate of a digital baseband input signal is increased using an upsampler to obtain an increased rate digital input signal. Predistortion is applied to the increased rate digital input signal using a DPD device to obtain a predistorted digital signal. The sampling rate of the predistorted digital signal is then decreased using a downsampler to obtain a lower-rate predistorted digital signal with a sampling rate below the increased rate of the upsampler (e.g. close to the bandwidth of a digital baseband input signal). A low pass filter may be provided to filter out-of-band signal components from the predistorted digital signal.