DPD Transceiver SERDES Interface for Faster PA Linearization
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Solution Overview
Problem
The increasing number of transmit chains and antennas in wireless communication systems, such as base stations, leads to significant power dissipation, latency, and non-linearity issues during digital pre-distortion (DPD) update and correction operations due to the large amount of data involved in DPD correction operations.
Innovation Solution
A transceiver circuit with a high-speed communication interface, utilizing serializer/de-serializer (SERDES) lanes for DPD-related data transfers, and truncation and concatenation circuitry to expedite data transfers between the host device and the transceiver, allowing for efficient DPD configuration profile and data sample transfers, thereby reducing latency and improving PA linearity and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DPD correction operations are performed on transmit data in systems with increasing number of transmit chains and antennas, then signal linearity is improved, but power dissipation and latency increase
Solution Approach 1:
The patent divides the DPD correction functionality into separate dedicated hardware modules for each transmit chain, allowing parallel processing of DPD corrections across multiple chains simultaneously. This segmentation enables the system to maintain signal linearity for multiple chains without proportionally increasing power dissipation in a single processing unit.
Solution Approach 2:
The patent implements pre-computation and caching of DPD correction parameters and lookup tables in on-chip memory before they are needed for actual transmit operations. By preparing DPD correction data in advance and storing it locally, the system reduces real-time computational power requirements and latency during active transmission.
2Measurement precision
If DPD update operations are performed with large amounts of data, then correction accuracy is improved, but processing time and latency increase
Solution Approach 1:
The patent segments the large DPD data sets into smaller manageable blocks that can be processed and transferred in parallel across multiple channels. The DPD correction data is divided into segments corresponding to different transmit chains and processing stages, enabling simultaneous handling of multiple data segments without overwhelming the processing bandwidth.
Solution Approach 2:
The patent introduces dedicated high-speed serial interfaces and buffer memory structures as intermediaries between the DPD computation source and the correction application points. These intermediary components facilitate efficient data transfer by providing staged buffering and parallel data paths, reducing the time required to move large DPD data sets through the system.
3Productivity
If more transmit chains and antennas are added to the system, then communication capacity is improved, but DPD processing complexity and power consumption increase
Solution Approach 1:
The patent implements a modular architecture where each transmit chain has its own dedicated DPD correction module with localized lookup tables and processing logic. This segmentation allows the system to scale to multiple transmit chains by simply adding identical modular units, rather than increasing the complexity of a centralized DPD processor. Each module operates independently with its own correction parameters.
Solution Approach 2:
The patent designs universal DPD correction modules that can be identically instantiated across multiple transmit chains, with each module capable of handling DPD corrections for its associated chain. This multi-functional approach allows the same hardware design to serve multiple purposes across different transmit paths, reducing overall system complexity compared to having custom DPD processing for each chain.
Data Source
AI summary
A system includes: a host processor; a transceiver coupled to the host processor; and a power amplifier coupled to an output of the transceiver. The transceiver includes a transmit chain with digital pre-distortion (DPD) logic configured to: perform DPD correction operations on transmit data received by the transmit chain; and output corrected transmit data based on the performed DPD correction operations, wherein the output corrected transmit data is provided to the power amplifier.