DPE Array Routing Using Global and Detailed Channel Paths

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Solution Overview

Problem

There is a lack of processor-based systems capable of compiling applications for execution on integrated circuits with heterogeneous data processing architectures, particularly in routing within data processing engine (DPE) arrays, where previous techniques fail to converge on solutions due to complexity and the inability to handle shared routing resources.

Innovation Solution

Implementing a processor-based system that uses integer linear programming (ILP) for global routing and a greedy algorithm for detailed routing, breaking down the routing process into simpler operations and identifying specific channels within global routes, which allows for faster route generation and compilation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional routing techniques are used in DPE arrays, then routing functionality is provided, but the system fails to converge on solutions due to complexity and inability to handle shared routing resources

Engineering Contradiction:
Improverouting solution convergenceVSAvoidrouting complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The routing process is divided into two distinct phases: global routing that determines the general path through the DPE array, and detailed routing that identifies specific channels within each DPE. This segmentation reduces the complexity of the overall routing problem by breaking it into smaller, more manageable sub-problems that can be solved sequentially.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The global routing phase performs preliminary action by establishing the general route through the array before detailed routing occurs. This preliminary path determination constrains the search space for detailed routing, enabling faster convergence and allowing the system to handle shared routing resources more effectively.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If detailed routing identifies specific channels within global routes, then routing precision is improved, but the compilation time increases

Engineering Contradiction:
Improverouting precisionVSAvoidcompilation time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

By separating global and detailed routing into distinct phases, the system achieves high routing precision without requiring the entire routing process to be solved simultaneously. The global phase establishes the path, and the detailed phase refines it with specific channel selections, maintaining precision while reducing overall computation time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The global routing phase determines the essential path information needed for routing, without fully resolving all channel details. This partial action approach provides sufficient precision for the application while avoiding the excessive computation time that would result from complete detailed routing of all possible channels.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10963615B1Data processing engine (DPE) array routing
Publication Date: 2021.03.30 XILINX INC
  • US10963615B1 patent drawing
  • US10963615B1 patent drawing
  • US10963615B1 patent drawing

AI summary

Some examples described herein relate to routing in routing elements. In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to model a communication network comprising switches interconnected in an array of data processing engines (DPEs), generate global routes of nets in the modeled communication network, generate detailed routes of the nets using the global routes, and translate the detailed routes to a file. Each of the switches has multiple input or output channels connected to another switch that are modeled as a single input or output edge, respectively, connected to the other switch. Each global route is generated through edge(s) of the switches. Each detailed route is generated comprising identifying one of the multiple input or output channels modeled by each edge through which the respective global route is generated.