DPE Array Compilation via Global and Detailed Mapping
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Solution Overview
Problem
No processor-based system was available to compile and map applications efficiently onto a data processing engine (DPE) array with a heterogeneous data processing architecture, leading to complexities and long runtime issues due to the lack of suitable compiler tools for generating binaries that can program hardened processor cores and communication networks.
Innovation Solution
Implementing a processor-based system with separate compiler modules capable of generating and compiling kernels with buffers mapped on hardened cores and memory groups of the DPE array, using global and detailed mapping techniques to efficiently assign programmable logic inputs/outputs and buffers to specific hardware components within the DPE array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate compiler modules with global and detailed mapping techniques are implemented, then compilation efficiency and runtime are improved, but device complexity increases
Solution Approach 1:
The compiler is divided into separate modules: a first compiler module that performs global mapping to assign program nodes to DPEs, and a second compiler module that performs detailed mapping to assign PLIOs to channels and buffers to memory banks. This segmentation allows each module to specialize in specific mapping tasks, improving overall compilation efficiency while managing complexity through modular design.
Solution Approach 2:
The global mapping is performed as a preliminary step before detailed mapping. By first assigning program nodes to DPEs and establishing a coarse-grained layout, the system prepares the foundation for subsequent detailed mapping operations. This preliminary action reduces the search space for the second compiler module, thereby improving compilation efficiency.
2Adaptability or versatility
If detailed mapping assigns PLIOs to channels and buffers to memory banks, then resource utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The detailed mapping process applies different mapping strategies to different resource types: PLIOs are mapped to specific channels in the interface, while buffers are mapped to specific memory banks. This local quality approach allows optimization for each resource type's specific characteristics and access patterns, improving overall resource utilization while maintaining appropriate precision requirements for each component.
3Speed
If global mapping assigns program nodes to DPEs, then processing speed is improved, but loss of information about detailed connections increases
Solution Approach 1:
The mapping process is segmented into two stages: global mapping that assigns program nodes to DPEs for parallel processing, and detailed mapping that restores connection information by assigning PLIOs to channels and buffers to memory banks. This segmentation allows the system to benefit from high-level parallel processing while subsequently recovering the necessary connection details for correct data flow.
Solution Approach 2:
Global mapping performs the preliminary assignment of program nodes to DPEs to enable parallel processing speedup. The loss of connection detail information is compensated by the subsequent detailed mapping step, which restores the necessary connectivity information through systematic assignment of interfaces and buffers, thus maintaining correctness while achieving speed benefits.
Data Source
AI summary
An example method for compiling by a processor-based system includes obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines; generating a global mapping of the program nodes based on a representation of the array of data processing engines; generating a detailed mapping of the program nodes based on the global mapping, the detailed mapping assigning input/outputs of programmable logic (PLIOs) of the device to channels in an interface of the array of data processing engines, the detailed mapping further assigning buffers of the application to individual memory banks in the array of data processing engines; and translating the detailed mapping to a file.