DPE Array Power Domains for Idle Engine Shutdown
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing hardware accelerators are separate components from CPUs, requiring off-chip communication which leads to inefficiencies in data transfer and power consumption.
Innovation Solution
Implementing a system on a chip (SoC) with data processing engines (DPEs) in multiple power and clock domains, allowing for selective deactivation of idle subsets while active subsets remain operational, utilizing on-chip communication techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hardware accelerator is implemented as a separate component from CPU, then device functionality is improved, but data transfer speed deteriorates due to off-chip communication
Solution Approach 1:
The patent merges the hardware accelerator and CPU into a single integrated circuit, eliminating the separate component architecture. This integration allows data processing engines to be disposed on the same substrate as the CPU, enabling direct on-chip communication and significantly improving data transfer speed while maintaining full device functionality.
2Adaptability or versatility
If hardware accelerator is implemented as a separate component from CPU, then device functionality is improved, but power consumption increases due to off-chip communication
Solution Approach 1:
The patent integrates the hardware accelerator with the CPU on the same chip substrate, replacing energy-intensive off-chip PCIe communication with efficient on-chip communication pathways. This merging reduces power consumption while preserving the hardware accelerator's data processing capabilities.
Solution Approach 2:
The patent segments the integrated circuit into distinct power domains, allowing independent power management of different functional blocks. This segmentation enables the system to deactivate unused portions of the hardware accelerator, reducing overall power consumption while maintaining necessary functionality.
3Productivity
If entire hardware accelerator is kept active, then processing capability is improved, but power consumption increases
Solution Approach 1:
The patent divides the hardware accelerator into multiple power domains, each capable of independent activation and deactivation. This segmentation allows the system to activate only the specific processing engines needed for current workloads, maintaining processing capability while minimizing power consumption by keeping unused domains in a low-power state.
Solution Approach 2:
The patent implements dynamic power management where the activation state of different power domains can be changed in real-time based on workload requirements. This dynamic approach allows the system to adapt processing capability to actual needs, avoiding the waste of keeping all engines active when only a subset is required.
Data Source
AI summary
Embodiments herein describe a hardware accelerator that includes multiple power or clock domains. For example, the hardware accelerator can include an array of data processing engines (DPEs) where different subsets of the DPEs (e.g., different columns, rows, or blocks) are disposed in different power or clock domains within the hardware accelerator. When one or more subsets of the DPEs are idle (e.g., the hardware accelerator has not assigned any tasks to those DPEs), the accelerator can deactivate the corresponding power or clock domain (or domains), which deactivates the DPEs in those domains while the DPEs in the other power or clock domains remain operational. As such, idle DPEs can be deactivated to conserve energy while DPEs with work can remain operational.