Data Processing Engine Array with Shared Memory Access
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Solution Overview
Problem
Current integrated circuit devices with programmable circuitry, such as FPGAs, face limitations in data processing efficiency and power consumption, particularly in implementing optimized digital signal processing architectures for operations like wireless radio and machine learning, while also requiring predictable data throughput and latency.
Innovation Solution
The integration of a plurality of data processing engines with shared memory access and a System-on-Chip interface block, including a memory mapped switch and stream switch, enables efficient data exchange and event broadcasting, optimizing digital signal processing while reducing power consumption and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a plurality of data processing engines with shared memory access are integrated, then data processing efficiency is improved, but device complexity increases
Solution Approach 1:
The device is segmented into multiple data processing engines (DPEs), each containing a core and memory module. This segmentation allows parallel processing operations while maintaining modular complexity management. Each DPE can be independently configured and operated, enabling efficient data processing through parallel execution of multiple data streams.
Solution Approach 2:
Multiple DPEs are merged into a unified array structure with shared interconnect resources. The memory mapped switch and stream switch provide shared communication infrastructure that reduces overall device complexity by eliminating redundant interconnect logic in each individual DPE. This merging allows efficient data exchange between DPEs while maintaining manageable system complexity.
2Speed
If optimized digital signal processing architectures are implemented, then processing speed is improved, but power consumption increases
Solution Approach 1:
The DPE array implements dynamic resource allocation where processing resources are activated only when needed. Each DPE can be independently enabled or disabled based on workload requirements, allowing the system to scale power consumption according to processing demands. The configurable nature of each DPE allows optimization of processing speed versus power consumption by activating only the necessary number of engines.
Solution Approach 2:
Each DPE is configurable through configuration data that can adjust operational parameters to optimize the trade-off between processing speed and power consumption. The memory module within each DPE can be configured with different sizes and access patterns, allowing optimization for specific workloads. This configurability enables the system to adapt parameters dynamically to achieve optimal performance per watt for different application scenarios.
3Area of stationary object
If multiple data processing engines are integrated in a compact array, then area usage is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Each DPE is designed as a universal module that can perform multiple functions through configuration. The core and memory module structure is replicated across all DPEs in the array, providing manufacturing simplicity through standardization. This universal design allows the same fabrication process to be used for all DPEs, reducing manufacturing precision requirements compared to highly customized processing elements. The interconnect structure also uses standardized routing patterns that simplify manufacturing.
4Reliability
If predictable data throughput and latency are ensured, then reliability is improved, but device complexity increases
Solution Approach 1:
The DPE array implements feedback mechanisms through the interconnect structure that monitor data flow between DPEs and adjust routing to maintain predictable throughput. The memory mapped switch and stream switch provide feedback paths that enable arbitration and flow control, ensuring that data throughput requirements are met. This feedback-based control allows the system to maintain reliable performance without requiring overly complex deterministic scheduling logic in each individual DPE.
Data Source
AI summary
A device includes a data processing engine (DPE) array having a plurality of data processing engines (DPEs) and a subsystem coupled to the DPE array. Each DPE of the plurality of DPEs is configurable to share data with one or more other DPEs of the plurality of DPEs using one or more of a plurality of data sharing techniques. The data sharing techniques include a core of a selected DPE accessing a memory module of an adjacent DPE via a memory interface of the selected DPE connected to a memory module of the adjacent DPE and the selected DPE accessing the memory module of a non-adjacent DPE using a DMA circuit and a stream switch of the selected DPE. The subsystem may be in a different die than the DPE array.