Hardware Accelerator Controller Synchronization
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Solution Overview
Problem
Implementing parallel hardware architectures for workload execution is challenging due to the need to synchronize workload components that must be executed in a particular order, often delayed by memory accesses, leading to synchronization issues.
Innovation Solution
A hardware accelerator array with a plurality of data processing engine (DPE) tiles arranged in columns, each equipped with a controller to manage execution and synchronize using local DM reads and remote DM writes through synchronization barriers, ensuring efficient execution across parallel controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel hardware architectures are used to execute workload components simultaneously, then execution efficiency is improved, but synchronization of workload components that need to be executed in a particular order becomes challenging
Solution Approach 1:
The system divides the workload into multiple segments or components that can be executed in parallel across different hardware elements. Each workload component can be independently scheduled and executed, allowing simultaneous processing while maintaining the ability to synchronize specific segments that require sequential execution through the control mechanism.
Solution Approach 2:
The control mechanism dynamically manages the execution schedule of workload components, adjusting the timing and synchronization points based on the specific requirements of each component. This dynamic control allows the system to optimize parallel execution while inserting synchronization barriers only where necessary, resolving the contradiction between parallel efficiency and synchronization complexity.
2Reliability
If workload components are synchronized to maintain execution order, then correctness is improved, but latency increases due to synchronization delays
Solution Approach 1:
Synchronization mechanisms are applied locally and selectively only to specific workload components that require ordered execution, rather than imposing global synchronization across all parallel operations. This localized approach maintains execution correctness for dependent components while allowing other independent components to proceed in parallel without synchronization delays.
Solution Approach 2:
The system maintains continuous execution of independent workload components without interruption from synchronization barriers, while only pausing specific dependent components when synchronization is truly necessary. This ensures that useful work continues uninterrupted wherever possible, minimizing overall latency while preserving execution correctness.
3Productivity
If memory accesses are performed during workload execution, then data processing is improved, but synchronization issues arise due to access delays
Solution Approach 1:
Data is pre-loaded into local buffers or caches before workload execution begins, or during periods when processing units are not actively computing. This preliminary data preparation reduces the need for synchronous memory accesses during critical execution phases, allowing workload components to proceed without synchronization delays while still maintaining data processing capability.
Data Source
AI summary
Embodiments herein describe a hardware accelerator with an array of data processing engines (DPEs) which includes a controller (e.g., a microcontroller) for multiple columns of the array. The controllers can be hardened circuitry that executes software code (or firmware) that controls the hardware accelerator. In one embodiment, the task of the controller is to control and orchestrate the functions performed by the hardware accelerator.