Data Processing Engine Core with Permuted Register Outputs
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Solution Overview
Problem
Existing data processing engines in integrated circuits face inefficiencies due to latency and memory usage issues when transferring data between cores, particularly through core-to-core interfaces.
Innovation Solution
A data processing engine core design featuring a register file, a multiply-accumulate (MAC) circuit, permute circuitry, and an instruction decoder that decodes very long instruction words (VLIW) to optimize parameter settings for both permute and MAC circuits, facilitating efficient data processing and reduction of latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data is transferred between cores through core-to-core interface, then data can be shared between cores, but latency increases and memory efficiency decreases
Solution Approach 1:
The patent merges the register files of multiple cores into a unified register file structure, allowing cores to access shared registers directly without inter-core data transfer. This eliminates the core-to-core interface latency while maintaining data sharing capability through the unified register architecture.
Solution Approach 2:
The unified register file serves multiple functions: it acts as shared data storage between cores, provides register file functionality for each core, and enables direct access without inter-core communication. This multi-functionality eliminates the need for separate core-to-core interfaces for data sharing.
2Productivity
If permute circuitry concatenates register file outputs, then data processing efficiency improves, but device complexity increases
Solution Approach 1:
The permute circuitry performs data reordering and concatenation operations in advance before data reaches the MAC circuit. By pre-processing the data arrangement through permute stages, the system optimizes data flow patterns without adding complex control logic during the main computation.
Solution Approach 2:
The permute circuitry acts as an intermediary between the register file and MAC circuit, handling the data rearrangement function. This intermediary layer simplifies the overall system by centralizing the complexity of data reordering in a dedicated block rather than distributing it throughout the architecture.
3Productivity
If VLIW instruction decoding is used, then parameter optimization for processor circuits is improved, but instruction decoding complexity increases
Solution Approach 1:
The VLIW instruction is segmented into distinct parameter fields that control different aspects of the processor circuits (permute circuit parameters, MAC circuit parameters, etc.). This segmentation allows independent optimization of each parameter set while maintaining a systematic decoding structure that manages complexity through organization.
Solution Approach 2:
The instruction decoder translates VLIW instructions into specific parameter values for the permute and MAC circuits. By changing the parameter settings based on decoded instructions, the system achieves flexible optimization without requiring complex hardware reconfiguration, as the same hardware adapts to different operations through parameter changes.
Data Source
AI summary
An example core for a data processing engine (DPE) includes a register file, a processor, coupled to the register file. The processor includes a multiply-accumulate (MAC) circuit, and permute circuitry coupled between the register file and the MAC circuit, the permute circuitry configured to concatenate at least one pair of outputs of the register file to provide at least one input to the MAC circuit. The core further includes an instruction decoder, coupled to the processor, configured to decode a very large instruction word (VLIW) to set a plurality of parameters of the processor, the plurality of parameters including first parameters of the permute circuitry and second parameters of the MAC circuit.