DPE Tile Architecture With DMA Shared Memory for Low-Latency Core Transfer
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Solution Overview
Problem
Existing integrated circuits face inefficiencies in data transfer between cores due to core-to-core interfaces that introduce latency and inefficient memory usage.
Innovation Solution
A data processing engine (DPE) architecture with direct memory access (DMA) circuitry, streaming interconnect, and memory-mapped interconnects, allowing direct data transfer between cores and shared memory banks, reducing latency and improving memory efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transferred between cores through a core-to-core interface, then data transfer can be achieved, but latency is introduced and memory usage becomes inefficient
Solution Approach 1:
The patent introduces a shared memory bank as an intermediary between cores, allowing direct memory access (DMA) circuitry to transfer data between cores without using the core-to-core interface. This mediator approach eliminates the latency associated with direct core-to-core communication while maintaining reliable data transfer capability.
Solution Approach 2:
The patent changes the data transfer dimension from direct core-to-core communication to core-to-memory-to-core transfers. By introducing the memory bank as an intermediate dimension, the system achieves more efficient data transfer through DMA operations, bypassing the latency-prone core-to-core interface.
2Ease of operation
If data is transferred through core-to-core interface, then communication between cores is enabled, but memory efficiency deteriorates
Solution Approach 1:
The shared memory bank serves as a mediator that enables core communication while improving memory efficiency. The DMA circuitry uses this intermediary to perform direct memory access operations, reducing unnecessary memory traffic and improving overall memory utilization efficiency compared to core-to-core interface transfers.
3Productivity
If direct memory access circuitry is added to enable efficient data transfer, then data transfer efficiency improves, but device complexity increases
Solution Approach 1:
The DMA circuitry is designed with multi-functionality, serving both local memory access and inter-core data transfer operations. This universal design allows a single circuit component to handle multiple types of data transfer operations, improving productivity without proportionally increasing device complexity.
Solution Approach 2:
The patent merges the DMA functionality with the existing memory interface infrastructure. By combining direct memory access capabilities with the shared memory bank architecture, the system achieves efficient data transfer without adding completely separate complex circuitry, thus improving productivity while controlling device complexity.
Data Source
AI summary
An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.