DPED Chopping Cancellation for Multi-Chip Clock Phase Alignment
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Solution Overview
Problem
Ensuring synchronized timing across chips in multi-chip setups is challenging and often requires expensive solutions, particularly in systems where precise timing and phase alignment are critical, such as in radio frequency and communication applications.
Innovation Solution
A duty-cycle and phase error detector (DPED) with chopping cancellation technique, utilizing multiplexers, logic gates, low-pass filters, and slicers to calibrate duty-cycles and phase errors of differential clocks, effectively managing high-frequency operations and mitigating layout path discrepancies and device mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional timing mechanisms are used to supply timing signals across chips, then timing synchronization can be achieved, but the solution becomes expensive and complex
Solution Approach 1:
The patent uses a duty-cycle and phase error detector that compares clock signals from different chips to detect timing errors, then generates correction signals. This copying and comparison approach allows inexpensive chips to achieve synchronized timing by referencing each other's clock signals rather than requiring expensive dedicated timing mechanisms.
Solution Approach 2:
The patent implements a feedback mechanism where the duty-cycle and phase error detector continuously monitors timing errors between clock signals and feeds back correction information to adjust the timing. This closed-loop feedback system enables automatic timing synchronization without requiring complex external timing mechanisms.
2Measurement precision
If precise timing mechanisms are implemented to ensure synchronized timing across chips, then timing accuracy improves, but cost increases
Solution Approach 1:
Instead of using expensive precision timing mechanisms, the patent copies clock signals between chips and uses standard duty-cycle and phase error detectors to achieve precise timing measurement and correction, significantly reducing system cost while maintaining timing accuracy.
Solution Approach 2:
The system performs self-calibration by having each chip monitor its own clock signal phase and duty cycle against reference signals from other chips, automatically detecting and correcting timing errors without requiring external expensive timing equipment.
3Measurement precision
If standard duty-cycle and phase error detectors are used without chopping cancellation, then device complexity is lower, but measurement precision deteriorates due to layout path discrepancies and device mismatches
Solution Approach 1:
The patent extracts and separates the chopping modulation function from the main detection circuit, using dedicated chopping switches that modulate the clock signals at a high frequency. This extraction allows the use of simple low-pass filters to remove the chopping frequency components, achieving high measurement precision while keeping the overall circuit manageable.
Solution Approach 2:
The patent implements periodic chopping modulation of the clock signals at a specific frequency, which allows timing errors to be detected at this modulation frequency. By using periodic action, the system can distinguish timing errors from static mismatches in layout paths and device parameters, significantly improving measurement precision.
Data Source
AI summary
A circuit may comprise a first multiplexer, a second multiplexer, a combination of logic gates, a third multiplexer, a first low-pas filter, and a second low-pass filter. The first multiplexer can be configured to receive and select a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. Respective phases of the first to fourth clock signals are related to each other. The second multiplexer can be configured to receive and select the first to fourth clock signals. The combination of logic gates may comprise a first logic gate and a second logic gate. The combination of logic gates can be coupled to the second multiplexer and can be configured to receive the second plurality of the first to fourth clock signals. The third multiplexer can be configured to receive and select the first to fourth outputs.