D-PHY Signal Transmission Circuit Synchronization
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Solution Overview
Problem
Conventional serialized signal transmission in D-PHY interfaces for mobile devices is error-prone and unstable due to synchronization challenges, leading to data loss and bit errors, especially when starting up the serial data connection.
Innovation Solution
A circuit arrangement and method that serialize single-ended high-speed data and differential low-power data to form a common signal stream, using a clock generator like a phase-locked loop to ensure synchronization before data transmission, and notifying the data source when the receiving arrangement is fully synchronized to prevent data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If serialized signal transmission is implemented to reduce the number of copper lines, then the quantity of transmission lines is reduced, but the reliability of data transmission deteriorates due to synchronization errors and data loss
Solution Approach 1:
The patent applies preliminary action by implementing a synchronization mechanism that activates before data transmission begins. The serializer waits for a synchronization signal from the deserializer before enabling data output, ensuring the receiving end is ready to correctly interpret the serialized stream. This prevents data loss and bit errors by establishing proper timing alignment in advance.
Solution Approach 2:
The patent implements feedback through a synchronization signal path where the deserializer monitors the received serialized data and sends a synchronization status back to the serializer. This feedback loop allows the transmitting end to know when the receiving end is properly synchronized, enabling reliable data transmission only when conditions are appropriate.
2Speed
If data transmission starts immediately after clock generation begins, then the transmission speed is improved, but data loss occurs due to incomplete synchronization of the transmission path
Solution Approach 1:
The patent prevents data loss by implementing preliminary synchronization before data transmission. The serializer includes logic to wait for a sync_ok signal from the deserializer before enabling data output. This ensures the receiving end's clock and data recovery circuitry is properly aligned and ready to capture data without loss, even though it delays transmission startup slightly.
3Device complexity
If conventional serialized transmission without synchronization control is used, then the device complexity is reduced, but the reliability deteriorates due to error-prone data transmission
Solution Approach 1:
The patent introduces an intermediary synchronization mechanism between the serializer and deserializer. The sync_ok signal acts as a mediator that coordinates the timing and state of both ends, ensuring they are properly aligned before and during data transmission. This intermediary control layer adds minimal complexity but significantly improves reliability by preventing synchronization errors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Guarantees error-free and stable serial transmission of D-PHY signals by synchronizing the transmission path before data is sent, avoiding data losses and bit errors, and ensuring reliable communication between data sources and sinks.
Implementation Method 1
a clock generator, in particular by at least one phase-locked loop (PLL), for example by at least one clock multiplier unit (CMU)
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3
AI summary
The invention relates to a circuit arrangement (A) and to a corresponding method which use both single-ended signals based on logic levels and differential, in particular common-mode-based signals, to continually transmit a serialized signal in an error-free, stable manner.