DPL Layout Decomposition via ILP Cost Function

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Double Patterning Lithography (DPL) techniques face challenges in reducing manufacturing costs and improving overlay control due to complex process flows and tight overlay requirements, particularly in feature splitting and line-edge errors, which are exacerbated by the need for precise layout decomposition and accurate metrology.

Innovation Solution

The use of integer linear programming (ILP), phase conflict detection (PCD), and node election bipartization (NBD) formulations for layout decomposition, along with a process-aware cost function that minimizes small line-ends and maximizes overlap at dividing points, to optimize DPL layout decomposition and reduce manufacturing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional DPL layout decomposition is used, then manufacturing cost increases due to complex process flows, but overlay control becomes more difficult

Engineering Contradiction:
Improvemanufacturing costVSAvoidoverlay control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The layout decomposition process segments the circuit layout into two separate masks by dividing features at dividing points. This segmentation allows each mask to have reduced pattern density, improving resolution while enabling independent optimization of each exposure step, thereby reducing overall manufacturing complexity and cost.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The method performs preliminary layout decomposition and feature splitting before actual lithography exposure. By pre-calculating dividing points and assigning features to masks in advance, the process eliminates the need for complex real-time overlay adjustment during manufacturing, reducing both cost and overlay control difficulty.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If features are split into multiple parts to resolve coloring conflicts, then overlay control requirements become tighter, but manufacturing cost increases

Engineering Contradiction:
Improveoverlay controlVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The method changes the parameter of feature spacing by introducing dividing points that create controlled gaps between features. This parameter change allows features that would otherwise conflict in coloring to be separated into different masks, reducing overlay control requirements while maintaining manufacturing feasibility.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The dividing points act as intermediaries between conflicting features. By introducing these intermediate division points, the method resolves coloring conflicts without requiring direct tight overlay control between all features, thereby reducing manufacturing cost while maintaining precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If line-ends are minimized in layout decomposition, then manufacturing cost decreases, but overlay accuracy becomes more critical

Engineering Contradiction:
Improvemanufacturing costVSAvoidoverlay accuracy
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The method extracts and removes unnecessary line-ends from the layout decomposition by carefully selecting dividing points that minimize feature splitting. This extraction reduces the number of critical overlay control points, thereby reducing manufacturing cost while maintaining acceptable overlay accuracy through strategic division rather than exhaustive splitting.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS8751974B2Layout decomposition for double patterning lithography
Publication Date: 2014.06.10 RGT UNIV OF CALIFORNIA
  • US8751974B2 patent drawing
  • US8751974B2 patent drawing
  • US8751974B2 patent drawing

AI summary

The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography (DPL). Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography (DPL) using integer linear programming (ILP) formulations. Embodiments of the invention meet a key optimization goals, which is to reduce the total cost of layout decomposition, considering the abovementioned aspects that contribute to cost of prior conventional DPL techniques. Embodiments of the invention provide integer linear programming (ILP), phase conflict detection (PCD) and node election bipartization (NBD) formulations for the optimization of DPL layout decomposition, with a process-aware cost function that avoids small jogging line-ends, and maximizes overlap at dividing points of polygons. The cost function can also make preferential splits at landing pads, junctions and long runs.