DPLL Clock Synthesizer Anti-Imaging for Phase Noise Harmonics
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Solution Overview
Problem
Existing Digital Phase Locked Loop (DPLL) clock synthesizers face challenges in effectively reducing spectrum images created during the upsampling process, leading to significant phase noise harmonics that are not adequately addressed by current anti-image filters.
Innovation Solution
The implementation of first-order linear interpolation filters in both the low and high rate clock domains within the DPLL, coupled with a hardware digital controlled oscillator (HDCO) and a software digital controlled oscillator (SDCO), to improve image reduction while maintaining system stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a DPLL is used to drive an HDCO generating output clock signals, then clock signal generation is achieved, but spectrum images and phase noise harmonics are created during the upsampling process
Solution Approach 1:
An anti-imaging filter is introduced as an intermediary component between the upsampling process and the HDCO. This filter mediates the harmful spectrum images generated during upsampling by filtering them out before they can affect the output clock signal, thereby resolving the contradiction between maintaining high clock generation rates and eliminating phase noise harmonics.
Solution Approach 2:
The harmful spectrum images and phase noise harmonics are extracted and removed from the signal path using the anti-imaging filter. This allows the useful clock signal to be maintained at high rates while the harmful components are separated and eliminated.
2Object-generated harmful factors
If anti-image filters are added to reduce phase noise harmonics, then image reduction is improved, but system complexity increases
Solution Approach 1:
The anti-imaging filter is designed with specific parameter choices (filter order, cutoff frequency, and placement in the signal path) that optimize the balance between image reduction performance and implementation complexity. By carefully selecting these parameters, effective phase noise suppression is achieved without unnecessarily complicating the system architecture.
3Object-generated harmful factors
If filtering is applied to reduce spectrum images, then phase noise is reduced, but risk of introducing instability increases
Solution Approach 1:
The filter design and placement are optimized to work within the feedback loop of the DPLL system. By positioning the anti-imaging filter appropriately and designing its characteristics to complement the loop filter, the system maintains stability while achieving effective image rejection. The feedback mechanism allows the system to self-correct and maintain stability despite the additional filtering stage.
Data Source
AI summary
A frequency synthesizer includes a hardware digital controlled oscillator (HDCO) running at a first clock rate fS for generating an output clock signal in response to a control input, and a digital phase locked loop (DPLL) responsive to a reference input sampled at a second clock rate fsamp, the first clock rate fS being N times greater than the second clock rate fsamp, The DPLL includes a loop filter and a software digital controlled oscillator (SDCO). A first, first order linear interpolation anti-imaging filter running at a clock rate higher than said second clock rate fsamp is coupled to an output of the loop filter for providing the control input to the HDCO. A second, first order linear interpolation anti-imaging filter running at said second clock rate coupled to the output of said loop filter to provide an input to said SDCO.