Time-Slotted DPLL Bus for Stable Multi-Loop Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In systems with multiple coupled digital phase-locked loops (DPLLs), the complexity of wiring connections grows rapidly, making it challenging to implement effective synchronization and frequency adjustment across multiple loops.
Innovation Solution
A time slotted bus system is introduced to couple multiple DPLLs, allowing them to exchange parameters using fixed time slots, minimize wiring connections, and enable users to program data broadcast times, while implementing separate data and address buses and bus handler modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple DPLLs are coupled using traditional wiring connections, then frequency offset adjustment and synchronization can be achieved, but the wiring complexity grows rapidly
Solution Approach 1:
Multiple separate wiring connections between DPLLs are merged into a single shared bus structure. The bus allows all DPLLs to communicate through common data and address lines, eliminating the need for dedicated point-to-point connections between each DPLL pair.
Solution Approach 2:
The shared bus serves multiple functions simultaneously: it carries data signals for frequency offset adjustment, address signals for selecting target DPLLs, and timing signals for synchronization. This multi-functional approach replaces multiple specialized wiring connections.
2Device complexity
If a shared bus is used to couple multiple DPLLs, then wiring complexity is reduced, but data exchange requires time multiplexing which may increase communication time
Solution Approach 1:
The bus operates using periodic time slots assigned to different DPLLs for data transmission. Each DPLL has dedicated time windows during which it can transmit or receive data without conflict, creating a structured periodic communication pattern that prevents collisions.
Solution Approach 2:
Address signals are transmitted before data signals to establish which DPLL should receive the upcoming data. This preliminary addressing allows receiving DPLLs to prepare their receivers in advance, minimizing actual data transfer time.
Data Source
AI summary
An apparatus includes a plurality of digital phase-locked loops and a time slotted bus. The time slotted bus is configured to couple the plurality of digital phase-locked loops. The plurality of digital phase-locked loops may be configured to exchange parameters between two or more of the plurality of digital phase-locked loops using one or more time slots of the time slotted bus.