Time-Slotted DPLL Bus for Low-Complexity Synchronization

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Solution Overview

Problem

In systems with multiple coupled digital phase-locked loops (DPLLs), the complexity of wiring connections grows rapidly, making it challenging to implement efficient synchronization and frequency adjustments across multiple loops.

Innovation Solution

A time slotted bus system is introduced to couple multiple DPLLs, allowing them to exchange parameters using fixed time slots, minimize wiring connections, and enable users to program data broadcast times, while implementing separate data and address buses and bus handler modules.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple DPLLs are coupled using traditional wiring connections, then frequency offset adjustment and synchronization can be achieved, but the wiring complexity grows rapidly

Engineering Contradiction:

Improvesynchronization stabilityVSAvoidwiring complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple individual wiring connections between DPLLs into a single shared bus structure. Instead of having separate point-to-point connections between each pair of DPLLs, all DPLLs are connected to a common bus that carries frequency offset and timing parameters for multiple loops simultaneously, dramatically reducing wiring complexity while maintaining synchronization capability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared bus serves multiple functions: it carries frequency offset parameters from sourcing DPLLs to receiving DPLLs, transmits timing synchronization signals, and supports parameter exchange among multiple DPLLs simultaneously. This multi-functional approach eliminates the need for separate dedicated connections for each synchronization task

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Device complexity

If a shared bus is used to couple multiple DPLLs, then wiring complexity is reduced, but data exchange between DPLLs requires time multiplexing

Engineering Contradiction:

Improvewiring complexityVSAvoidparameter exchange timing

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent implements time-division multiplexing where the shared bus operates in periodic time slots, with each DPLL allocated specific time windows for transmitting and receiving parameters. Sourcing DPLLs transmit frequency offset parameters in designated time slots, and receiving DPLLs receive and process these parameters in subsequent time slots, creating a rhythmic, periodic data exchange pattern that organizes bus access efficiently

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The continuous bus operation is segmented into discrete time slots, with each time slot dedicated to specific DPLL communications. This segmentation prevents data collisions and ensures orderly parameter exchange by dividing the bus bandwidth into manageable temporal segments, each serving specific synchronization tasks

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10476509B2Time slotted bus system for multiple coupled digital phase-locked loops

Publication Date: 2019.11.12 RENESAS ELECTRONICS AMERICA INC

AI summary

An apparatus includes a plurality of digital phase-locked loops and a time slotted bus. The time slotted bus is configured to couple the plurality of digital phase-locked loops. The plurality of digital phase-locked loops may be configured to exchange parameters between two or more of the plurality of digital phase-locked loops using one or more time slots of the time slotted bus.