DPLL Calibration Circuit for Wide-Range PVT Frequency Tracking
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Solution Overview
Problem
Conventional digital phase locked loops (DPLLs) face challenges in matching input and output signal phases due to high dynamic range requirements, which increase the size of the digitally controlled oscillator (DCO) and lead to failures in tracking variations in process, voltage, and temperature (PVT) and frequency modulation techniques.
Innovation Solution
A calibration system for DPLLs that includes a calibration circuit and a DCO with a bias generator, digital-to-analog converter (DAC), and oscillator circuit, which generates a bias signal based on an input bias code and digital signal to produce an analog signal, allowing the DCO to internally generate a feedback signal and adjust the dynamic range without increasing the number of bits in the digital signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the dynamic range of the DPLL is increased to cover a high frequency range, then the frequency coverage is improved, but the number of bits required in the N-bit digital signal increases, causing the size of the DCO to increase
Solution Approach 1:
The patent changes the parameter of bias current magnitude to control the frequency range of the DCO. By adjusting the bias current magnitude based on a bias code, the DCO can operate across a wide frequency range without requiring an increased number of bits in the digital signal, thus maintaining a compact size while achieving high adaptability.
Solution Approach 2:
The DCO is designed to perform multiple functions: frequency generation, frequency tuning, and automatic frequency calibration. The frequency calibration function, enabled by the bias generator and comparator, allows the DCO to self-adjust its operating frequency to match the reference signal, eliminating the need for external calibration circuits and reducing overall system complexity.
2Device complexity
If the dynamic range of the DPLL is reduced to decrease the number of bits in the digital signal, then the DCO size is reduced, but the DPLL fails to match the phases of the input and output signals due to frequency variations from PVT and frequency modulation
Solution Approach 1:
The patent implements a feedback mechanism where the output signal of the DCO is fed back to the comparator, which compares it with the reference signal. Based on the comparison result, the calibration circuit adjusts the bias code to the bias generator, which in turn adjusts the bias current magnitude to the DCO. This closed-loop feedback system enables the DCO to automatically correct frequency deviations caused by PVT variations and frequency modulation, maintaining accurate phase matching while using a reduced number of bits.
Solution Approach 2:
The DCO incorporates an internal frequency calibration capability through the bias generator and comparator circuitry. The system performs self-calibration by automatically detecting frequency mismatches and adjusting its own bias current, eliminating the need for external calibration circuits and enabling reliable phase matching even with a compact DCO design.
3Manufacturing precision
If an external bias generator is used to provide a bias signal for frequency calibration, then the frequency calibration function is achieved, but the DPLL is unable to track the variations in PVT associated with the DPLL
Solution Approach 1:
The patent merges the frequency calibration function with the PVT tracking capability by integrating the bias generator and comparator directly into the DCO. This unified structure allows the same circuit to perform both initial frequency calibration and continuous tracking of PVT variations, as the feedback loop continuously monitors the output frequency and adjusts the bias current in real-time to compensate for environmental changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the DPLL to maintain phase lock across varying PVT conditions and frequency modulation techniques without the need for external bias signals, reducing the size of the DCO and improving its ability to track frequency variations.
Implementation Method 1
The DAC is coupled with the bias generator, and configured to receive a digital signal and the bias signal. The DAC is further configured to convert the digital signal to generate an analog signal based on the bias signal.
Implementation Method 2
The oscillator circuit is coupled with the DAC, and configured to receive the analog signal and generate an output signal. A frequency of the output signal is based on an amplitude of the analog signal.
Data Source
AI summary
A calibration system of a digital phase locked loop (DPLL) includes a calibration circuit and a digitally controlled oscillator (DCO). The calibration circuit is configured to receive an input signal and a feedback signal, and generate a digital signal, based on a frequency of the input signal, a frequency of the feedback signal, and an input bias code. The DCO is configured to receive the input bias code and the digital signal, and generate a bias signal based on the input bias code. The DCO is further configured to generate an analog signal based on the bias signal and the digital signal, and generate the feedback signal such that the frequency of the feedback signal is based on an amplitude of the analog signal.