DPLL Reference Clock Dithering for Lower DCO Phase Noise
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Solution Overview
Problem
Digital phase locked loops (DPLLs) face challenges in reducing quantization noise in digitally controlled oscillators (DCOs), which degrades output jitter and phase noise, and existing dithering techniques are either ineffective or impractical due to increased power and area requirements or introduce additional noise.
Innovation Solution
A digital phase locked loop architecture that linearizes the response of a bang-bang phase and frequency detector (PFD) using an adjustable delay line to modulate the reference clock, injecting controlled jitter shaped to higher frequencies, thereby improving jitter performance and reducing phase noise without additional power or area costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If DCO resolution is increased by reducing minimum frequency step, then quantization noise is reduced, but DCO area and power dissipation increase
Solution Approach 1:
The patent changes the dithering frequency parameter to match the DCO operating frequency, transforming the noise spectral distribution. By setting fDITH = fDCO, the quantization noise is shaped to fall at spectral zeros, reducing in-band noise without requiring increased DCO resolution, thereby avoiding additional power dissipation and area overhead.
Solution Approach 2:
The patent converts the harmful quantization noise into a beneficial effect by using dithering at a specific frequency that aligns with the DCO operating frequency. The noise energy is redirected to spectral zeros where it does not degrade performance, effectively using the noise itself to achieve noise reduction in the signal band.
2Object-affected harmful factors
If conventional uniform dithering is used, then DCO frequency is modulated, but quantization noise is only reduced by spreading over wider band, achieving minimal improvement
Solution Approach 1:
The patent changes the critical parameter of dithering frequency from conventional values (fREF/4 or fREF/8) to match the DCO operating frequency. This parameter change transforms the noise spectral shape, concentrating noise energy at spectral zeros rather than uniformly spreading it, achieving superior noise reduction with the same circuit area.
3Object-affected harmful factors
If dithering frequency is set to conventional values (fREF/4 or fREF/8), then noise is spread over wider band, but in-band noise reduction is limited to approximately 7 dB
Solution Approach 1:
The patent changes the dithering frequency parameter to fDCO, which fundamentally alters the noise spectral distribution. This causes quantization noise to fall at spectral zeros of the DCO transfer function, achieving dramatically better in-band noise reduction compared to conventional dithering frequencies that only provide ~7 dB improvement.
4Measurement precision
If DCO quantization noise is reduced by increasing frequency resolution, then phase noise improves, but device complexity increases
Solution Approach 1:
The patent converts the quantization noise problem into a solved issue by using frequency-domain shaping through optimal dithering. Instead of increasing DCO resolution to reduce noise, the method shapes the noise spectrum to fall at zeros, achieving low phase noise with the existing DCO structure and maintaining simple device complexity.
Data Source
AI summary
A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.