DPLL Clock Synchronization for Packet Delay Variation
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Solution Overview
Problem
Current methods for time and frequency synchronization in packet networks, particularly in telecom networks, face challenges in achieving sub-microsecond accuracy due to packet delay variation and loss, which affect clock noise and jitter, especially in the absence of reference clocks or GPS services.
Innovation Solution
A digital phase locked loop (DPLL) system is employed in slave devices to process timestamps from master clocks, estimating skew and offset to synchronize slave clocks with master clocks, thereby providing both time and frequency signals with reduced clock noise, using IEEE 1588 PTP messages and recursive estimation techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If packet-based clock recovery mechanisms are used to synchronize slave clocks to master clocks over packet networks, then time and frequency synchronization can be achieved, but packet delay variation and packet losses cause clock noise and jitter, degrading synchronization accuracy
Solution Approach 1:
The patent segments the clock recovery function into two independent modules: a timestamp-based clock recovery mechanism for frequency synchronization and a phase-locked loop (PLL) for time synchronization. This segmentation allows each module to optimize for its specific function, with the PLL filtering out clock noise and jitter from the timestamp-based frequency estimates, thereby resolving the contradiction between achieving synchronization and maintaining reliability against packet network impairments.
Solution Approach 2:
The patent introduces a phase-locked loop (PLL) as an intermediary between the timestamp-based clock recovery mechanism and the slave clock. The PLL acts as a filter that processes the frequency estimates from the timestamp mechanism, attenuating clock noise and jitter before updating the slave clock. This intermediary resolves the contradiction by protecting the synchronization process from the harmful effects of packet delay variation and losses.
2Adaptability or versatility
If adaptive timing techniques are used to reconstruct timing signals without reference clocks or GPS services, then end-to-end time and frequency transfer can be achieved, but the absence of external reference clocks causes propagation of wander to the receiver clock signal
Solution Approach 1:
The patent merges two clock recovery approaches: timestamp-based clock recovery for frequency transfer and phase-locked loop for time transfer. By combining these mechanisms, the system achieves both adaptability (independent operation without external references) and stability (through PLL filtering of wander and noise). The merged system resolves the contradiction by leveraging the strengths of both approaches while mitigating their individual weaknesses.
Solution Approach 2:
The patent implements feedback through the phase-locked loop, which continuously monitors the phase and frequency differences between the reconstructed timing signal and the slave clock, then adjusts the slave clock accordingly. This feedback mechanism attenuates propagated wander and maintains clock signal stability, resolving the contradiction between independent operation and signal stability.
3Measurement precision
If IEEE 1588 PTP messages are exchanged for clock synchronization, then time and frequency information can be distributed across the network, but the protocol does not define specific clock recovery mechanisms, requiring additional implementation complexity
Solution Approach 1:
The patent implements a universal clock recovery mechanism that handles both time and frequency synchronization through a unified architecture combining timestamp-based recovery and phase-locked loop. This multi-functional design resolves the contradiction by providing a single implementation that achieves precise time and frequency distribution without requiring separate mechanisms, thereby reducing overall device complexity while maintaining high precision.
Data Source
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AI summary
This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.