DPLL Master Clock Redundancy for Stable Oscillator Switchover
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Solution Overview
Problem
Digital phase locked loops (DPLLs) in telecom/datacom systems are vulnerable to master clock failures, particularly from crystal oscillators, which have a higher failure rate than integrated circuits, leading to system downtime and potential bit errors when the input reference clock is unavailable.
Innovation Solution
Implementing a digital phase locked loop arrangement with master clock redundancy using multiple crystal oscillators, a multiplexer, and a controller to switch between active and redundant oscillators upon failure or performance degradation, ensuring minimal disruption and frequency stability by compensating for frequency differences during switchover.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single master clock source is used to drive the DPLL, then the device complexity is low, but the reliability is poor due to higher failure rate of crystal oscillators
Solution Approach 1:
The patent implements preliminary action by providing redundant master clock sources (XO1, XO2) that are pre-configured and monitored before failure occurs. The clock monitors continuously check the status of each oscillator, and the controller is ready to switch to a backup source immediately upon detecting a failure or performance degradation, thus preventing system downtime without requiring complex real-time decision-making circuits
Solution Approach 2:
The patent applies beforehand cushioning by having standby clock sources ready to compensate for potential failures. The redundant oscillators act as a cushion against the high failure rate of crystal oscillators, ensuring continuous operation. The frequency compensation mechanism also provides a cushion against frequency drift by correcting deviations before they cause system errors
2Reliability
If redundant master clock sources are implemented, then the reliability is improved, but the device complexity increases due to additional components and control logic
Solution Approach 1:
The patent implements self-service by enabling the system to automatically monitor, detect, and switch between clock sources without external intervention. The clock monitors continuously assess the health of each oscillator, and the controller autonomously performs switching and frequency compensation operations, eliminating the need for manual configuration or complex external control circuitry
Solution Approach 2:
The controller serves multiple functions: it monitors clock sources, detects failures, performs switching operations, and executes frequency compensation. This multi-functionality consolidates what could be separate complex subsystems into a single integrated unit, reducing overall device complexity while maintaining high reliability
3Reliability
If switching between clock sources is performed, then the reliability is maintained during failure, but frequency stability may be affected during switchover
Solution Approach 1:
The patent implements feedback through frequency monitoring and compensation mechanisms. When switching between clock sources, the system measures the frequency of the new source and applies corrective adjustments to maintain the desired output frequency. This feedback loop ensures that frequency stability is preserved during and after switchover operations, preventing bit errors in timed devices
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting frequency parameters during switchover. The controller modifies the operating parameters of the DPLL to accommodate the characteristics of the newly selected clock source, ensuring seamless transition without compromising frequency stability or causing system errors
Data Source
AI summary
Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating clock signals is selected to drive the DCO. The performance of the crystal oscillators is monitored, and the DCO is switched from being driven by a previously selected crystal oscillator to a newly selected crystal oscillator upon loss of a clock signal from the previously selected crystal oscillator or when the performance of the previously selected crystal oscillator falls below a predetermined acceptable level.