Digital PLL Clock Alignment Using Reflected Signal Feedback
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Solution Overview
Problem
Existing digital phase lock loops (DPLLs) require external reference signals to align chip internal clocks, which can be impractical due to the need for careful board-level layout to avoid uncorrectable synchronization differences, especially when synchronizing clocks between multiple chips.
Innovation Solution
The use of point-to-point un-terminated transmission lines with half the impedance of the output clock drivers and high-threshold input buffers in a clock distribution block allows for automatic phase alignment of clock signals across multiple chips without external references, utilizing feedback signals and variable delay lines to synchronize clock transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external reference signals are used to synchronize clocks between multiple chips, then clock alignment can be achieved, but board-level layout complexity increases and uncorrectable synchronization differences may occur
Solution Approach 1:
The patent extracts the external reference signal requirement by implementing autonomous phase alignment using only locally available clock signals. Each chip generates its own phase alignment control signals based on its received clock signal, eliminating the need for external reference signals and their associated layout constraints.
Solution Approach 2:
Each chip performs self-phase-alignment by autonomously generating control signals (UP/DOWN) based on comparison of its received clock signal with an internally generated signal. The system is self-regulating, requiring no external intervention or reference signals for synchronization.
2Measurement precision
If external reference signals are used for multi-chip clock synchronization, then proper clock alignment can be ensured, but the system becomes more vulnerable to layout-induced synchronization errors
Solution Approach 1:
The patent removes the system's dependence on external reference signals that are susceptible to layout-induced errors. By using autonomous phase alignment with locally generated control signals, the system eliminates the harmful effect of board-level layout variations on synchronization precision.
Solution Approach 2:
The patent implements feedback mechanisms where each chip continuously monitors its received clock signal phase and autonomously generates UP/DOWN control signals to adjust its internal clock phase. This closed-loop feedback system maintains precise alignment without being affected by external layout variations.
3Reliability
If traditional DPLL methods are used with external references, then clock synchronization can be achieved, but the system requires additional external components and increased interconnection complexity
Solution Approach 1:
The patent extracts and eliminates the requirement for external reference signals and associated interconnection infrastructure. The autonomous phase alignment method achieves synchronization using only the existing clock distribution network, removing unnecessary external components and simplifying the overall system architecture.
Solution Approach 2:
The patent makes the clock distribution network universally functional by enabling it to serve both clock delivery and autonomous phase alignment purposes. The same interconnections used for clock distribution also carry the feedback information needed for self-phase-alignment, eliminating the need for separate external reference signal paths.
Data Source
AI summary
This disclosure describes methods and techniques using Digital Phase Lock Loops (DPLLs) within a source chip to automatically phase align a plurality of clock signals at a plurality of clock pins on a plurality of target chips of varying distances and corresponding delays from the source chip by using each transmitted clock signal's reflected signal as a tuning reference.