DPLL Reference Clock Switching for Power Control Without Relocking
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Solution Overview
Problem
Existing digital phase locked loops (DPLLs) face challenges in changing the frequency of the reference clock without significantly affecting loop control, which is crucial for power consumption management in portable communication devices.
Innovation Solution
A programmable frequency device that generates a reference clock from a set of distinct frequencies while maintaining the same temporal relationship of triggering edges, minimizing disruption to the phase locked loop operation and allowing for efficient power management by adjusting the reference clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the frequency of the reference clock is lowered to reduce power consumption, then power consumption is reduced, but the loop control of the DPLL is significantly affected
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing the frequency selection control signal with the reference clock before switching between different frequency clocks. The circuit asynchronously receives the frequency selection control signal, then synchronizes it to the reference clock edge, ensuring that the switch occurs at a predetermined time aligned with the clock cycle. This preliminary synchronization prevents disruption to the DPLL loop control while enabling power-saving frequency reduction.
2Use of energy by moving object
If the frequency of the reference clock is changed using prior approaches, then power consumption can be controlled, but a substantial amount of time is required for the frequency change and relocking operation
Solution Approach 1:
The patent prepares the frequency switch in advance by synchronizing the control signal to the reference clock edge before the actual frequency change occurs. This preliminary alignment ensures that when the frequency switch is executed, the DPLL is already prepared and can maintain loop control continuity, eliminating the need for time-consuming relocking operations that occur in prior approaches.
3Use of energy by moving object
If the frequency of the reference clock is changed without synchronization, then power consumption can be reduced, but the temporal relationship of triggering edges changes and disrupts loop control
Solution Approach 1:
The patent synchronizes the frequency selection control signal to the reference clock edge before executing the frequency switch. This preliminary synchronization ensures that the temporal relationship of triggering edges is maintained across frequency changes, as the switch occurs precisely at a predetermined clock edge rather than asynchronously, thereby preserving loop control stability.
Data Source
AI summary
An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks. The apparatus further comprises a phase locked loop (PLL), such as a digital PLL (DPLL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal. By maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, the continual and effective operation of the phase locked loop (PLL) is not significantly disturbed while changing the reference clock. This may be used to control the power consumption of the apparatus.