DPLL Reference Clock Switching for Low-Power Loop Stability
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Solution Overview
Problem
Existing digital phase locked loops (DPLLs) face challenges in efficiently managing power consumption while changing the frequency of the reference clock, as prior methods often disrupt loop control and take substantial time to relock, which is not acceptable in many applications.
Innovation Solution
A programmable frequency device is used to generate a reference clock by selecting from a set of distinct frequency clocks, maintaining the same temporal relationship of triggering edges, thereby minimizing disruption to the phase locked loop and allowing for efficient power management by adjusting the reference clock frequency without affecting loop control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the frequency of the reference clock is lowered to reduce power consumption, then power consumption is reduced, but the loop control of the DPLL is significantly affected
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing the phase of the new reference clock with the existing loop state before switching. The system adjusts the phase of the incoming reference clock to match the current loop phase, ensuring that the transition does not disrupt loop control stability. This allows frequency changes while maintaining reliable loop operation.
2Use of energy by moving object
If the frequency of the reference clock is changed using prior approaches, then power consumption can be adjusted, but the relocking operation takes a substantial amount of time
Solution Approach 1:
The system performs preliminary phase alignment of the new reference clock with the current loop state before the actual frequency switch occurs. By pre-synchronizing the phases and preparing the loop for the transition, the relocking time is significantly reduced compared to conventional approaches that require complete relocking after frequency changes.
Solution Approach 2:
The patent implements dynamic frequency switching by allowing the reference clock frequency to change while maintaining continuous loop operation. The system dynamically adjusts the reference clock frequency based on power management requirements while using phase synchronization to ensure smooth transitions, enabling the loop to adapt to frequency changes without substantial relocking delays.
3Use of energy by moving object
If the frequency of the reference clock is changed, then power consumption can be optimized, but the temporal relationship of triggering edges changes, disrupting loop control
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the phase of the new reference clock to match the temporal relationship required by the loop before switching occurs. This phase synchronization ensures that the triggering edges maintain their proper temporal relationships with other loop signals, preventing disruption to loop control while enabling frequency changes for power optimization.
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AI summary
An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks. The apparatus further comprises a phase locked loop (PLL), such as a digital PLL (DPLL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal. By maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, the continual and effective operation of the phase locked loop (PLL) is not significantly disturbed while changing the reference clock. This may be used to control the power consumption of the apparatus.