Digital PLL Computation Spreading for RF Spur Reduction
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Solution Overview
Problem
Conventional all-digital phase locked loop (ADPLL) circuits in wireless communication systems are inflexible and prone to significant silicon area overhead, leading to increased silicon area and power consumption, and generate unacceptable RF spurs due to dedicated hardware designs, making them unsuitable for multi-standard wireless applications and difficult to reconfigure.
Innovation Solution
A software-based phase locked loop (PLL) architecture utilizing a reconfigurable calculation unit (RCU) that performs all atomic operations sequentially at a high processor clock frequency, allowing for time-sharing and oversampling to reduce silicon area and spur generation, enabling easier reconfiguration and multi-standard support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated hardware design is used for ADPLL, then reliability is improved, but device complexity and silicon area increase
Solution Approach 1:
The patent employs a reconfigurable calculation unit (RCU) that can dynamically adapt its structure and operation to perform different ADPLL functions. The RCU uses a state machine architecture with programmable logic elements that can be configured via control signals to implement various phase detector algorithms, loop filter operations, and frequency synthesis functions, replacing multiple dedicated hardware blocks with a single universal processing unit.
Solution Approach 2:
The patent introduces dynamic reconfigurability to the ADPLL architecture through the RCU, which can change its operational characteristics in real-time. The state machine within the RCU can be reprogrammed to adjust loop bandwidth, change phase detector types, and modify filtering characteristics, allowing the system to adapt to different wireless standards and operating conditions without hardware changes.
2Speed
If dedicated hardware blocks are used for each function, then processing speed is improved, but silicon area and power consumption increase
Solution Approach 1:
The patent consolidates multiple separate dedicated hardware blocks (phase detector, loop filter, frequency divider, etc.) into a single integrated reconfigurable calculation unit. The RCU combines arithmetic logic units, accumulators, filters, and control logic into one unified structure that can be dynamically configured to perform different functions, significantly reducing the total silicon area while maintaining processing capability.
Solution Approach 2:
The patent divides the ADPLL computation into discrete atomic operations that can be executed sequentially by the RCU. The phase detector output, loop filter updates, and frequency synthesis calculations are broken down into individual computational steps that the state machine can execute in a predetermined sequence, enabling time-multiplexed operation that reduces hardware requirements while maintaining speed.
3Productivity
If computation is performed within a single clock period, then productivity is improved, but harmful factors (spurs) increase
Solution Approach 1:
The patent introduces a multi-cycle computation approach where the RCU executes ADPLL atomic operations over multiple clock periods rather than completing all calculations in a single cycle. The state machine progresses through different computational stages (phase detection, frequency calculation, loop filter update) in sequential clock cycles, spreading out the switching activity and reducing peak current transients that cause RF spurs.
Solution Approach 2:
The patent performs preliminary computations and data preparation in earlier clock cycles before the final frequency synthesis operation. The RCU pre-calculates phase error values, prepares loop filter coefficients, and validates input data in advance, allowing the critical frequency synthesis step to execute with minimal switching activity and reduced spur generation.
Data Source
AI summary
A novel and useful apparatus for and method of spur reduction using computation spreading in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over and completed within an entire PLL reference clock period. Each computation being performed at a much higher processor clock frequency than the PLL reference clock rate. This functions to significantly reduce the per cycle current transient generated by the computations. Further, the frequency content of the current transients is at the higher processor clock frequency. This results in a significant reduction in spurs within sensitive portions of the output spectrum.