Digital DPLL Coarse Locking With Cycle Slip Saturation
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Solution Overview
Problem
Digital phase-locked loops (DPLLs) face challenges in achieving quick frequency lock during the acquisition mode due to cycle slipping, which can prolong the duration of this mode and prevent frequency lock, leading to inefficiencies in data transmission and increased energy consumption.
Innovation Solution
The implementation of a digital phase-locked loop circuit with a coarse time-to-digital converter (TDC) and a coarse digital loop filter (DLF) that detects cycle slipping and modifies the phase error to reduce its impact, using a saturation circuit to saturate the phase error to a pre-determined value when cycle slipping is detected, and employing a frequency divider circuit to generate clock signals by dividing the output of a digitally controlled oscillator (DCO) by a dividing factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DPLL operates in acquisition mode to achieve frequency lock from an initial frequency far from target, then frequency lock is achieved, but the duration of acquisition mode is prolonged due to cycle slipping
Solution Approach 1:
The patent applies preliminary action by performing cycle slipping detection and phase error modification before the phase error can cause harmful effects. The TDC continuously monitors phase error and detects cycle slipping events in advance, modifying the phase error value proactively to prevent acquisition mode prolongation. This anticipatory approach allows the DPLL to maintain reliable frequency lock achievement while avoiding the time loss that would otherwise occur during cycle slipping events.
2Reliability
If the DPLL operates in acquisition mode for extended period due to cycle slipping, then frequency lock may eventually be achieved, but energy consumption increases
Solution Approach 1:
The patent implements feedback by continuously monitoring phase error for cycle slipping detection and dynamically modifying phase error values based on detected cycle slipping events. The TDC provides real-time feedback about cycle slipping conditions to the phase error calculation, enabling the system to adaptively correct phase error values. This feedback mechanism ensures reliable frequency lock achievement while minimizing energy consumption by preventing prolonged acquisition mode operation caused by undetected cycle slipping.
3Reliability
If cycle slipping is detected and phase error is modified to reduce its impact, then robustness against cycle slipping is enhanced, but device complexity increases
Solution Approach 1:
The patent applies merging by integrating cycle slipping detection and phase error modification functions directly into the existing TDC and phase error calculation logic of the DPLL. Rather than adding separate dedicated circuits for cycle slipping detection and correction, the patent combines these functions with the existing phase measurement and processing infrastructure. This integrated approach enhances robustness against cycle slipping while minimizing the increase in device complexity by reusing existing circuit components.
Data Source
AI summary
A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.