Digital PLL Computation Spreading With Dithering for Spur Reduction
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Solution Overview
Problem
Conventional all-digital phase locked loop (ADPLL) circuits in wireless communication systems face challenges in supporting multi-standard applications due to their fixed hardware design, which limits reconfigurability and leads to significant silicon area overhead, increased current transients, and unacceptable RF spurious tones.
Innovation Solution
A software-based phase locked loop architecture with a reconfigurable calculation unit (RCU) that performs all atomic operations within a single reference clock cycle, using a processor-based approach to reduce silicon area and minimize current transients by oversampling and function sharing, and incorporates dithering to further reduce frequency spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed hardware-based ADPLL design is used, then the circuit provides stable operation, but it cannot support multi-standard applications and requires numerous time-consuming design changes
Solution Approach 1:
The patent transforms the static hardwired ADPLL into a dynamic software-reconfigurable system. The phase detector, loop filter, and other components are implemented as software modules that can be loaded and unloaded dynamically to support different wireless standards (GSM, UMTS, Bluetooth, WiFi), enabling the same hardware platform to adapt to multiple standards without physical reconfiguration.
Solution Approach 2:
The patent creates a universal ADPLL architecture that can perform multiple functions by loading different software configurations. A single processor-based platform can serve as phase detector, loop filter, frequency synthesizer, and other PLL components for various standards, eliminating the need for separate hardwired circuits for each standard.
2Reliability
If hardwired circuit design is committed to physical implementation, then the design is fixed, but any modification requires numerous time-consuming steps in ASIC creation process
Solution Approach 1:
The patent replaces the mechanical/physical reconfiguration process of ASIC design with software-based reconfiguration. Instead of going through lengthy ASIC creation steps (timing closure, physical design, manufacturing), the system loads new software images to implement design changes, reducing the modification process from months to minutes while maintaining design stability through verified software implementations.
3Speed
If computations are performed within a single reference clock period, then the processing speed is maintained, but current transients increase causing RF spurious tones
Solution Approach 1:
The patent introduces dithering that periodically varies the software loop duration around the reference clock period. By adding random wait cycles (0, 1, or 2 cycles) to the software loop, the computation is spread over multiple reference clock periods, which reduces the amplitude of current transients and consequently reduces RF spurious tones while maintaining the average processing speed.
Solution Approach 2:
The patent changes the timing parameter of computation by introducing variable wait cycles in the software loop. The loop duration is dynamically adjusted by adding random delays (0-2 reference clock cycles), which spreads the computational load over time and reduces peak current transients that cause frequency spurs, while the processor clock frequency remains significantly higher than the reference clock frequency.
Data Source
AI summary
A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over a PLL reference clock period wherein each computation is performed at a much higher processor clock frequency than the PLL reference clock rate. This significantly reduces the per cycle current transient generated by the computations. The frequency content of the current transients is at the higher processor clock frequency which results in a significant reduction in spurs within sensitive portions of the output spectrum. Further reduction in spurs is achieved by dithering the duration of the software loop of atomic operations and/or by randomly shuffling one or more non-data dependent instructions within each iteration of the software loop.