Digital Phase-Locked Loop with Dual Tracking for Lower Phase Noise
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Solution Overview
Problem
Digital phase-locked loops (DPLLs) face performance degradation due to noise in output signals, leading to reduced signal characteristics and stability.
Innovation Solution
A DPLL design incorporating two tracking units with bangbang phase detectors and delay-controlled delay lines, along with a digitally controlled oscillator and digital loop filter, to generate and control the output signal based on phase differences between reference and feedback signals, reducing noise and improving signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional DPLL is used to generate output clock signals, then the basic phase-locked loop function is achieved, but the output signal experiences noise degradation leading to reduced signal characteristics and stability
Solution Approach 1:
The DPLL is divided into two separate tracking units: a first tracking unit that generates a delayed reference signal by tracking the feedback signal, and a second tracking unit that generates the output signal by tracking the delayed feedback signal using the delayed reference signal. This segmentation allows each unit to perform specialized tracking functions, reducing cumulative noise and improving signal stability.
Solution Approach 2:
The delayed reference signal generated by the first tracking unit serves as an intermediary signal that mediates between the original reference signal and the feedback signal. This intermediary allows the second tracking unit to operate with reduced noise by comparing the delayed feedback signal against a reference that has already been adjusted for phase variations.
2Measurement precision
If tracking operations are performed to reduce phase noise, then signal characteristics improve, but the device complexity increases due to additional tracking units and components
Solution Approach 1:
Both tracking units use identical core components (bang-bang phase detectors and delay-controlled delay lines) that perform multiple functions. The first tracking unit generates the delayed reference signal while the second generates the output signal, both using the same type of phase detection and delay control mechanisms, thereby reducing overall circuit complexity through component reuse and standardization.
3Object-generated harmful factors
If noise reduction techniques are implemented in the DPLL, then output signal characteristics improve, but power consumption may increase
Solution Approach 1:
The patent replaces traditional analog phase-locked loop mechanisms with a fully digital implementation using bang-bang phase detectors and delay-controlled delay lines. This digital substitution eliminates the need for complex analog filtering and noise reduction circuits that would consume significant power, achieving noise reduction through digital signal processing instead.
Data Source
AI summary
Provided are a digital phase-locked loop (DPLL) having improved signal characteristics, and a method of operating the DPLL. The DPLL includes a first tracking unit configured to receive a reference signal and a feedback signal that is generated by feeding back an output signal of the DPLL, track the feedback signal, and output a delayed reference signal, and a second tracking unit configured to receive a delayed feedback signal generated by delaying the feedback signal, and the delayed reference signal, and generate an output signal of the DPLL, of which a frequency is controlled according to a phase difference between the delayed feedback signal and the delayed reference signal.