DPLL Frequency Multiplier with Duty-Cycle Calibration for Low Spurious Output
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Solution Overview
Problem
The quality of output signals in a clock frequency multiplier circuit is heavily reliant on the duty cycle of the input reference clock signal, leading to spurious signals when the duty cycle is not 50%, compromising radio frequency communications systems.
Innovation Solution
A frequency multiplier in a digital phase-locked loop circuit that includes a clock controller to determine the duty cycle error of the reference clock signal, using a clock calibration circuit to adjust the duty cycle to 50% through a control signal, and a clock frequency multiplier to generate a calibrated clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional frequency multiplier using cascaded frequency multiplying circuits is used, then frequency multiplication can be achieved, but phase error accumulates and jitter increases at the output
Solution Approach 1:
The frequency multiplication process is divided into multiple stages, with each stage performing partial frequency multiplication. The output of each stage is fed back to the input of the same stage through a feedback path, allowing phase error correction at each segment rather than accumulating across all stages. This segmentation approach breaks the cumulative phase error problem into manageable segments that can be corrected locally.
Solution Approach 2:
A feedback path is introduced that feeds the output signal back to the input of each frequency multiplying circuit stage. This feedback mechanism allows the system to detect and correct phase errors at each stage by comparing the feedback signal with the input signal, thereby preventing phase error accumulation and reducing jitter in the final output.
2Reliability
If feedback paths are added to correct phase errors, then phase error accumulation is reduced, but circuit complexity increases
Solution Approach 1:
The feedback path serves multiple functions simultaneously: it provides phase error correction, enables automatic frequency control, and maintains synchronization across all frequency multiplying stages. By making the feedback mechanism multi-functional, the patent reduces the need for separate correction circuits, thereby limiting the increase in overall circuit complexity while achieving effective phase error reduction.
3Speed
If multiple frequency multiplying circuits are cascaded to achieve high frequency multiplication, then output frequency increases, but jitter increases proportionally
Solution Approach 1:
Phase error correction is performed preliminarily at each frequency multiplying stage before the signal proceeds to the next stage. By correcting phase errors early in each segment rather than allowing them to accumulate across all stages, the system maintains lower jitter even at high output frequencies. This preliminary correction action prevents the exponential growth of jitter that would otherwise occur with cascaded multiplication.
Data Source
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AI summary
A frequency multiplier, a digital phase-locked loop circuit, and a frequency multiplication method are provided. The frequency multiplier includes: a clock controller, configured to: receive an output signal of a time-to-digital converter in the digital phase-locked loop circuit, and generate a control signal based on a duty cycle error of the output signal; a clock calibration circuit, configured to: receive a reference clock signal, calibrate a duty cycle of the reference clock signal based on the control signal, and output a calibrated clock signal; and a clock frequency multiplier, configured to: receive the calibrated clock signal, multiply a frequency of the calibrated clock signal, and output a frequency multiplied signal to the time-to-digital converter.