Digital Phase-Locked Loop Frequency Error Correction
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Solution Overview
Problem
Existing disk drive systems face challenges in accurately positioning the head over data tracks due to vibrations that cause frequency errors, leading to difficulties in locking onto the read signal and maintaining precise head positioning.
Innovation Solution
The implementation of a digital phase-locked loop (DPLL) with a frequency induced phase error correction mechanism, which learns and adjusts for phase errors during the reading of periodic patterns, enables the timing recovery circuit to synchronize the sampling clock with the data rate, even in the presence of substantial frequency errors, by using a zero-phase start block and integrating phase errors to reset and converge the phase interpolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional phase-locked loop is used for timing recovery, then the system can achieve basic synchronization, but it cannot accurately lock onto the read signal when substantial frequency errors are present due to vibrations
Solution Approach 1:
The patent replaces the traditional analog phase-locked loop with a digital phase-locked loop that uses digital signal processing. The DPLL samples the read signal at multiple phases, digitally computes phase errors using correlation techniques, and applies digital correction to the sampling clock. This substitution enables accurate phase measurement even when substantial frequency errors are present due to disk vibrations, thereby improving both measurement precision and locking reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the DPLL continuously measures the phase error between the sampling clock and the actual data transitions, then adjusts the sampling clock phase accordingly. The phase error is computed by correlating the sampled signal with expected transition patterns, and this error feedback drives the phase correction to achieve and maintain accurate synchronization despite frequency variations caused by vibrations.
2Speed
If the sampling clock is not synchronized with the data rate, then frequency errors can occur, but achieving synchronization is difficult when vibrations affect disk rotation frequency
Solution Approach 1:
The patent makes the sampling clock dynamic by allowing its phase to be continuously adjusted based on real-time phase error measurements. The DPLL structure enables the sampling clock to adapt its timing to match the actual data rate even when that rate varies due to vibrations. The system transitions from a fixed-frequency clock to a dynamically adjustable clock that can track frequency variations, thereby achieving and maintaining synchronization under varying operating conditions.
Solution Approach 2:
The patent changes the phase parameter of the sampling clock dynamically to achieve synchronization. By measuring the phase difference between expected and actual data transitions, the system adjusts the sampling clock's phase parameter in real-time. This parameter adjustment allows the system to adapt to frequency variations caused by vibrations and maintain accurate synchronization with the data stream.
Data Source
AI summary
A disk drive is disclosed comprising a head actuated over a disk comprising a sector including a periodic pattern and sector data. The sector is read with the head to generate a read signal which is sampled at a sampling frequency with a signal sampler to generate signal samples. The signal samples representing the periodic pattern are processed to measure a frequency induced phase error based on kδ where k represents a signal sample index and δ is a fraction of 2π. The signal samples representing the sector data are processed to generate a data phase error. The data phase error is adjusted in response to the frequency induced phase error to generate an adjusted data phase error, and the signal sampler is controlled in response to the adjusted data phase error.