DPLL Loop Filter Value Retention for Low Power Mode Transitions
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Solution Overview
Problem
Digital phase-locked loops (DPLLs) experience long startup times when transitioning from low power mode to normal mode, leading to inaccuracies in clock frequency and potential timing violations due to undershoot or overshoot, which is problematic in applications like switching converters that require immediate and accurate clock frequency restoration.
Innovation Solution
A DPLL system with a loop filter that maintains its value during low power mode transitions, allowing the digitally-controlled oscillator (DCO) to output a clock signal based on the maintained loop filter value when transitioning back to normal mode, ensuring immediate and accurate clock frequency restoration without significant delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the DPLL is turned off during low power mode to reduce current consumption, then power efficiency is improved, but the startup time when transitioning back to normal mode increases significantly
Solution Approach 1:
The loop filter value is preserved before entering low power mode, preparing the system in advance so that when the DPLL restarts, it can immediately use the pre-saved loop filter value to generate the correct output frequency without requiring a lengthy startup sequence or frequency calibration period
2Device complexity
If the DPLL is restarted from a loop filter reset value, then the system can be simplified, but the output clock frequency experiences significant undershoot or overshoot
Solution Approach 1:
The loop filter value storage function is extracted and maintained separately during low power mode, allowing the DPLL to be fully disabled for power savings while preserving the critical frequency information needed for accurate restart, thereby avoiding frequency undershoot or overshoot without complicating the overall system architecture
3Ease of operation
If the DPLL output clock frequency is allowed to have undershoot or overshoot during startup, then the startup process is simplified, but timing violations occur in clock domains
Solution Approach 1:
By preserving the loop filter value before entering low power mode, the system prepares the exact frequency settings needed for restart in advance, ensuring that when the DPLL wakes up, it can immediately output the correct frequency without transient undershoot or overshoot that would cause timing violations in dependent clock domains
Data Source
AI summary
A system includes a digital phase-locked loop (DPLL) having a loop filter and a digitally-controlled oscillator (DCO). The system also includes a clock generator coupled to an output of the DPLL, and a plurality of clock domains coupled to the clock generator. The DPLL is configured to transition between a low power mode and a normal mode, wherein the loop filter is configured to maintain its value when the DPLL transitions from the normal mode to the low power mode. The DCO is configured to output a DCO clock signal based on the maintained loop filter value when the DPLL transitions from the low power mode to the normal mode.