DPLL Loop Gain Calibration for PVT-Stable Bandwidth
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Solution Overview
Problem
Digital phase locked loops (DPLLs) in semiconductor devices are affected by process-voltage-temperature (PVT) variations, leading to non-uniform loop gain and bandwidth, which can lower the yield of semiconductor devices.
Innovation Solution
Incorporating a loop gain calibrator (LGC) and a multiplier circuit to generate test signals and adjust the multiplication coefficient, compensating for PVT variations in the digital-controlled oscillator (DCO), ensuring uniform loop gain and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a digital phase locked loop (DPLL) is used instead of an analog PLL, then the device occupies less space and operates at lower voltage, but the loop gain and bandwidth become non-uniform due to PVT variations
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the multiplication coefficient in the feedback path based on detected PVT variations. The system measures actual PVT conditions and modifies the feedback signal parameters accordingly to maintain uniform loop gain and bandwidth despite environmental changes
Solution Approach 2:
The patent implements feedback by introducing a detection mechanism that monitors PVT variations and feeds this information back to adjust the multiplication coefficient. This closed-loop approach ensures that the DPLL maintains uniform characteristics by continuously compensating for detected variations
2Reliability
If the multiplication coefficient is adjusted to compensate for PVT variations, then loop gain uniformity is improved, but the device complexity increases due to additional calibration circuits
Solution Approach 1:
The patent applies self-service by enabling the DPLL system to automatically detect its own PVT variations and self-correct by adjusting the multiplication coefficient without external intervention. The calibration circuit monitors the system's own performance and performs autonomous compensation
3Productivity
If PVT variations are compensated for in real-time, then yield is enhanced, but the operating complexity and calibration requirements increase
Solution Approach 1:
The patent applies preliminary action by performing calibration operations in advance during manufacturing or initialization. The system pre-determines appropriate multiplication coefficients for different PVT conditions, so that during normal operation, the device can quickly switch between pre-calibrated settings without complex real-time adjustments
Data Source
AI summary
A semiconductor device includes a time-to-digital converter (TDC) that receives a reference frequency signal and a feedback frequency signal, and outputs a first digital signal indicating a time difference between the reference frequency signal and the feedback frequency signal; a digital loop filter (DLF) that outputs a second digital signal generated by filtering the first digital signal; a multiplier circuit that outputs one of a third digital signal and a final test signal, the third digital signal generated by performing a multiplication operation on the second digital signal using a multiplication coefficient; a digital-controlled oscillator (DCO) that generates an oscillation signal having a frequency based on the output one of the third digital signal and the final test signal; and a loop gain calibrator (LGC) that receives the oscillation signal, generates a pair of test signals, and determines the multiplication coefficient using the pair of test signals.