DPLL Oscillator Calibration Using Discrete Capacitor Banks
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Solution Overview
Problem
Existing frequency calibration methods for oscillators in communication devices face challenges in achieving high frequency accuracy without increasing cost or power consumption, particularly due to temperature variations and oscillator degradation over time.
Innovation Solution
A frequency calibration circuit comprising a first oscillator with high frequency accuracy, a second oscillator with lower frequency accuracy, and a digital phase-locked-loop circuit that adjusts the capacitance of discrete type capacitor banks to synchronize and calibrate the phase of the second clock signal with the first clock signal, using the second oscillator as a digital control oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a TCXO is used to achieve high frequency accuracy of plus or minus 10 ppm, then frequency accuracy is improved, but price and power consumption increase
Solution Approach 1:
The system divides the oscillator functions into two segments: a first oscillator (32.768 kHz) with high frequency accuracy for RTC operations, and a second oscillator (32 MHz) with lower accuracy for internal circuit control. This segmentation allows each oscillator to be optimized for its specific purpose, avoiding the need for a high-power TCXO for all functions.
Solution Approach 2:
A frequency calibration circuit acts as an intermediary between the two oscillators. It uses a digital phase-locked loop to calibrate the second oscillator's frequency based on the first oscillator's accurate time base, thereby achieving high frequency accuracy for the second oscillator without requiring it to be a power-consuming TCXO.
2Use of energy by moving object
If a crystal oscillator is used instead of a TCXO, then power consumption is reduced, but frequency accuracy deteriorates to plus or minus 20 ppm
Solution Approach 1:
The frequency calibration circuit implements a feedback mechanism where the first oscillator's accurate signal is used to detect and correct frequency deviations in the second oscillator. The digital phase-locked loop continuously monitors and adjusts the second oscillator's frequency, ensuring it maintains plus or minus 10 ppm accuracy despite temperature changes, while the second oscillator itself remains a low-power crystal type.
Solution Approach 2:
The system changes the operating parameters of the second oscillator through digital control. By adjusting the capacitance of discrete type capacitor banks based on calibration data stored in a lookup table, the oscillator's frequency is dynamically tuned to compensate for temperature variations and aging effects, maintaining high accuracy without increasing power consumption.
3Adaptability or versatility
If discrete type capacitor banks are used in the second oscillator, then layout area increases, but frequency adjustability is improved
Solution Approach 1:
The capacitor bank is segmented into multiple discrete capacitors that can be individually switched. This segmentation allows for fine-grained frequency adjustment by selecting specific capacitor combinations, achieving precise frequency calibration while optimizing the layout by placing only the necessary capacitors based on the required adjustment range.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves frequency accuracy equivalent to the first clock signal, maintaining target accuracy despite temperature changes and oscillator degradation, while minimizing power consumption and layout area, and reducing costs by employing discrete type capacitor banks effectively.
Implementation Method 1
a discrete type capacitor bank having a plurality of discrete type capacitors whose capacitances change in binary and being configured to hold a digital control signal, capacitances of the plurality of discrete type capacitors being changed in accordance with the held digital control signal such that a capacitance of whole of the discrete type capacitor bank changes
Data Source
AI summary
In the frequency calibration circuit, the digital phase-locked-loop circuit repeats a calibration operation involving outputting the digital control signal corresponding to a time difference between the first clock signal which is input from the first oscillator and has a first frequency accuracy, and the second clock signal which is input from the second oscillator and has a second frequency accuracy lower than the first frequency accuracy, changing the capacitance of the discrete type capacitor bank in accordance with the digital control signal using the second oscillator as a digital control oscillator, and changing an oscillation frequency of the second clock signal in accordance with the capacitance of the discrete type capacitor bank, thereby calibrating a phase of the second clock signal to a phase of the first clock signal.