DPLL Phase Shift Control for Fast LO Frequency Switching
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Solution Overview
Problem
Existing wireless communication technologies face challenges in rapidly scanning channels for reliable RSSI measurements due to the long lock-in time required by analog oscillators for frequency adjustments.
Innovation Solution
A method and apparatus that apply phase shift to a digital phase-locked loop (DPLL) circuit to adjust the frequency of a local oscillator signal used for down-conversion, allowing for rapid frequency adjustments without leaving the frequency-lock state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an analog oscillator is used to generate the local oscillator signal, then the frequency can be adjusted, but the lock-in time becomes long, slowing down the channel scanning process
Solution Approach 1:
The patent replaces the analog oscillator with a digital phase-locked loop (DPLL) circuit that uses digital signal processing to generate the local oscillator signal. This substitution of digital for analog technology enables rapid frequency adjustments through digital control without the long lock-in times characteristic of analog oscillators, directly resolving the contradiction between frequency adjustment capability and lock-in time.
Solution Approach 2:
The patent applies phase shift to the DPLL circuit to adjust the frequency of the local oscillator signal. By changing the phase shift parameter digitally, the system can rapidly switch between different frequencies during channel scanning without requiring lengthy lock-in periods, thus improving channel scanning speed while minimizing time loss.
2Adaptability or versatility
If frequent frequency adjustments are made for channel scanning, then channel coverage is improved, but the number of frequency-locking operations increases, extending processing time
Solution Approach 1:
The patent replaces the traditional frequency-locking mechanism with a digital phase-shifting approach in the DPLL circuit. This allows the system to perform frequent frequency adjustments for comprehensive channel scanning while maintaining rapid response times, as digital phase shifts occur much faster than analog frequency-locking operations.
Solution Approach 2:
The patent pre-configures the DPLL circuit with phase shift capabilities that allow immediate frequency adjustments. By having the digital control mechanism ready and the phase shift parameters pre-established, the system can rapidly switch between channels without requiring time-consuming frequency-locking operations for each channel transition.
3Productivity
If rapid frequency switching is implemented for fast RSSI measurement, then measurement speed is improved, but frequency accuracy may be compromised
Solution Approach 1:
The patent uses a digital phase-locked loop circuit instead of an analog oscillator, leveraging digital signal processing to maintain frequency accuracy during rapid switching. The DPLL's digital control mechanism ensures that even during fast frequency transitions for RSSI measurement, the frequency remains precisely controlled through digital phase adjustment rather than analog tuning.
Solution Approach 2:
The phase-locked loop incorporates feedback control that continuously monitors and adjusts the phase and frequency of the local oscillator signal. This feedback mechanism ensures that rapid frequency switching for fast RSSI measurement does not compromise frequency accuracy, as the loop continuously corrects any deviations to maintain precise frequency alignment.
Data Source
AI summary
A wireless communication device includes a receiver circuit, a phase shift control circuit, and a digital phase-locked loop (DPLL) circuit. The receiver circuit includes a down-converter circuit that is used to apply down-conversion to an input signal according to a local oscillator (LO) signal. The phase shift control circuit is used to generate a phase shift signal. The DPLL circuit is used to generate the LO signal locked to an initial frequency under a frequency-lock state. In response to the phase shift signal, the DPLL circuit is further used to make the LO signal have a different frequency without leaving the frequency-lock state.