DPLL Sawtooth Ramp Generation With Fast Chirp Settling
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Solution Overview
Problem
Digital phase-locked loops (DPLLs) face challenges in generating sawtooth ramps with fast settling times, leading to significant frequency errors and prolonged settling times, which limit their performance in radar applications.
Innovation Solution
A DPLL configuration with a digital loop filter comprising a proportional path, sampling circuit, and integral path, including an accumulator that resets upon a new chirp, and a digitally controlled oscillator, which generates a sawtooth ramp signal with a settling time of less than 1 microsecond by adjusting the oscillator tuning word based on sampled values and resetting the accumulator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional DPLL configuration is used to generate sawtooth ramps, then the system maintains standard loop filter operation, but the settling time becomes excessively long (greater than 1 microsecond) causing significant frequency errors
Solution Approach 1:
The loop filter proactively resets the accumulator to an initial value in association with the end of a chirp, before the next chirp begins. This preliminary action prevents the accumulation of phase errors and ensures the sawtooth ramp signal is ready for the next frequency sweep without prolonged settling time, thereby maintaining frequency accuracy while reducing settling time to less than 1 microsecond
Solution Approach 2:
The system uses a time-to-digital converter coupled in a feedback path between the oscillator output and loop filter input to monitor the phase/frequency deviation. This feedback mechanism allows the loop filter to detect when the oscillator has drifted and triggers appropriate corrections, ensuring frequency accuracy is maintained while enabling faster settling through the reset mechanism
2Loss of time
If the loop filter operates without resetting the accumulator, then the integration function is maintained, but the settling time is prolonged due to accumulated phase errors
Solution Approach 1:
The accumulator is reset periodically in association with the end of each chirp cycle. This periodic action synchronizes with the sawtooth ramp generation, allowing the loop filter to maintain its integration function during each chirp while systematically clearing accumulated phase errors at the end of each cycle, thereby reducing settling time without adding continuous complexity
Solution Approach 2:
The loop filter transitions between two operational states: during the chirp, it performs normal integration to track frequency; at the end of the chirp, it dynamically resets the accumulator to an initial value. This dynamic switching allows the system to maintain integration functionality while periodically eliminating accumulated errors, achieving fast settling without requiring a fundamentally different loop filter architecture
Data Source
AI summary
Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.