DPLL Sample Rate Conversion for SDR Power Reduction
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Solution Overview
Problem
Current Software Defined Radio (SDR) systems face challenges with high complexity and power consumption, particularly in SDR terminals, due to the need for supporting multiple sample rates and dynamic frequency adjustments, which complicates hardware configuration and increases energy usage.
Innovation Solution
A sample rate conversion apparatus and method utilizing a Digital Phase Locked Loop (DPLL) and frequency divider to generate a variable clock with integer and fractional scaling, reducing the dynamic range and step size of the PLL, thereby simplifying the system and lowering power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple sample rates are supported through software reconfiguration, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal sample rate conversion architecture where a single DPLL-based frequency scaling unit can generate multiple sample rates (e.g., 30.72 MHz, 38.4 MHz, 46.08 MHz, 61.44 MHz) by adjusting control parameters. This multi-functional design eliminates the need for separate hardware circuits for each sample rate, thereby improving adaptability while reducing overall device complexity
Solution Approach 2:
The patent changes the operational parameters of the DPLL frequency scaling unit to achieve different sample rates. By modifying the frequency division ratio and control values rather than changing hardware configuration, the system can dynamically adapt to different sample rate requirements, resolving the contradiction between adaptability and complexity
2Adaptability or versatility
If dynamic frequency adjustment is implemented for multiple communication standards, then versatility is improved, but power consumption increases
Solution Approach 1:
The patent employs a universal frequency scaling unit based on DPLL that can serve multiple communication standards (WCDMA, CDMA2000, GSM, etc.) through software reconfiguration. This single multi-functional unit replaces multiple dedicated frequency adjustment circuits, reducing the overall power consumption while maintaining versatility across different communication standards
Solution Approach 2:
The patent replaces traditional hardware-based frequency synthesis methods with a software-controlled DPLL system. This substitution allows frequency adjustment through parameter changes rather than physical hardware switching, significantly reducing power consumption while maintaining the ability to support multiple communication standards
3Measurement precision
If high precision sample rate conversion is achieved, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces a DPLL-based frequency scaling unit as an intermediary between the fixed-frequency clock source and the variable sample rate requirements. This intermediary component provides precise frequency control through its phase-locked loop mechanism, achieving high sample rate accuracy without requiring complex direct synthesis circuits
Solution Approach 2:
The DPLL frequency scaling unit inherently provides its own frequency stabilization and precision control through its closed-loop feedback mechanism. This self-service capability eliminates the need for additional complex control circuits to maintain sample rate accuracy, resolving the contradiction between precision and complexity
Data Source
AI summary
A method for converting a sample rate in a Software Defined Radio (SDR) communication system is provided. The method includes setting a sampling frequency range depending on a maximum sampling frequency and a minimum sampling frequency so as to enable support of a plurality of sample rates; if a required sampling frequency is set, determining a control value for converting the maximum sampling frequency to the required sampling frequency; and receiving a signal having the maximum sampling frequency, and converting the signal having the maximum sampling frequency to a signal having the required sampling frequency depending on the control value. The control value is determined taking into account a maximum sampling frequency for setting the sampling frequency range.