DPLL Spur Cancellation Circuit for Multiple Intermodulation Sources
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Solution Overview
Problem
Digital phase locked loop (PLL) circuits in wireless communication systems face challenges in simultaneously canceling spurs from multiple sources, particularly those arising from the intermodulation of clock signals with the crystal oscillator and voltage-controlled oscillator, which degrade system performance and constellation error.
Innovation Solution
A calibration scheme is implemented within the DPLL circuit to dynamically cancel spurs by measuring and injecting cancellation tones at multiple locations, using a spur cancellation block with multiplexers and demultiplexers to automatically track phases, amplitudes, and frequency drifts, ensuring robustness across various fabrication, voltage, and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clocks run simultaneously to generate multiple clock signals with different frequencies, then the system functionality and clock diversity are improved, but spurs are generated through intermodulation with the crystal oscillator and VCO that degrade system performance
Solution Approach 1:
The patent measures the spur signals and generates cancellation tones that convert the harmful spur interference into beneficial cancellation signals. The cancellation tones are injected into the DPLL circuit to actively neutralize the spurs, transforming the harmful intermodulation products into opportunities for active cancellation and performance improvement.
Solution Approach 2:
The patent introduces cancellation tones as intermediary signals that mediate between the harmful spurs and the desired clean output. These cancellation tones act as intermediate elements that interfere destructively with the spurs, effectively eliminating the harmful interference without directly modifying the original clock signals or oscillator circuits.
2Reliability
If a calibration scheme measures and injects cancellation tones to cancel spurs, then spur cancellation performance is improved, but the device complexity increases due to additional measurement and injection circuits
Solution Approach 1:
The patent combines the spur measurement and cancellation tone injection functions into an integrated calibration scheme within the DPLL circuit. The measurement circuits and injection circuits are merged with the existing DPLL architecture, sharing common components such as the phase detector, charge pump, and loop filter, thereby reducing overall complexity while maintaining effective spur cancellation.
Solution Approach 2:
The calibration scheme is designed to be universal, capable of canceling spurs from multiple sources simultaneously. The same measurement and injection infrastructure handles spurs from the reference path, VCO path, and intermodulation products, making the circuit multi-functional and reducing the need for separate cancellation mechanisms for each spur source.
3Measurement precision
If cancellation tones are injected to track phases, amplitudes, and frequency drifts, then the cancellation accuracy is improved, but the ease of operation deteriorates due to automatic tracking requirements
Solution Approach 1:
The calibration scheme implements self-service through automatic tracking of phase, amplitude, and frequency drift. The measurement circuits continuously monitor the spur characteristics and automatically adjust the cancellation tones without requiring manual intervention. The system serves itself by detecting deviations and correcting them through the charge pump and loop filter, maintaining high cancellation accuracy autonomously.
Solution Approach 2:
The patent employs feedback mechanisms where the measured spur signals are fed back to adjust the cancellation tones in real-time. The phase detector and charge pump create a feedback loop that continuously tracks phase and frequency variations, automatically adjusting the cancellation signals to maintain optimal cancellation accuracy despite environmental variations and drift.
4Reliability
If spurs are canceled from both reference and VCO paths simultaneously, then the overall system performance is improved, but the device complexity increases due to multiple cancellation paths
Solution Approach 1:
The patent segments the spur cancellation function into separate measurement and injection paths for the reference and VCO, allowing independent optimization of each path. The measurement circuits for reference spurs and VCO spurs are segmented and processed separately, then combined in the cancellation tone generation, enabling targeted cancellation without requiring a completely separate system for each path.
Data Source
AI summary
A circuit for phase locked loop (PLL) multiple spur cancellation includes multiple spur cancellation circuits and a number of multiplexers that are coupled to respective input ports of the spur cancellation circuits. The circuit further includes a number of demultiplexers that are coupled to respective output ports of the spur cancellation circuits. Each spur cancellation circuit can cancel a spur associated with a spur source, and input nodes of the multiplexers and output nodes of the demultiplexers are coupled to different connection points of a PLL circuit.