DPLL Time-to-Digital Converter With Integrated Filter Clocking
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Solution Overview
Problem
Digital phase-locked loops (DPLLs) face issues due to asynchronous digital bits from the time-to-digital converter (TDC) being out of sync with the input reference clock, requiring an additional synchronization stage that increases delay, jitter, cost, and area in the design.
Innovation Solution
Incorporating clock generation circuitry within the TDC to generate a filter clock synchronized with both the input reference clock and feedback clock, eliminating the need for an external synchronization circuit by triggering clock pulses from the last-received pulses of both clocks, thus synchronizing phase error values with the filter clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate synchronization circuit is employed between TDC and DLF, then the reference clock is synchronized to the data being passed as digital bits, but this adds another clock cycle which creates delay and jitter in the output signal
Solution Approach 1:
The patent merges the synchronization function into the TDC by having the TDC generate the filter clock that directly clocks the DLF. This eliminates the separate synchronization circuit and its associated delay, while maintaining proper synchronization between the reference clock and digital bits through the TDC's internal clock generation mechanism.
2Reliability
If a separate synchronization circuit is employed between TDC and DLF, then synchronization is achieved, but this also adds cost and area to the DPLL design
Solution Approach 1:
The synchronization functionality is merged into the existing TDC block by having it generate the filter clock internally. This eliminates the need for a separate synchronization circuit, reducing both area and cost while maintaining synchronization accuracy through the TDC's inherent capability to generate properly synchronized clock signals.
Solution Approach 2:
The TDC is given a dual function: it performs time-to-digital conversion and simultaneously generates the filter clock for the DLF. This multi-functionality eliminates the need for dedicated synchronization circuitry, reducing overall device complexity and area while maintaining all required functions.
3Reliability
If a separate synchronization circuit is employed, then data synchronization is achieved, but the number of clock cycles increases
Solution Approach 1:
By merging the synchronization function into the TDC's clock generation mechanism, the patent eliminates the additional clock cycle introduced by a separate synchronization stage. The TDC generates the filter clock that directly clocks the DLF, achieving data synchronization in the same clock cycle without additional delays.
Data Source
AI summary
A time-to-digital converter (TDC) circuit includes phase error calculation circuitry to: determine phase error values based on a time difference between a input reference clock and a feedback clock of a digital phase-locked loop (DPLL) circuit, the input reference clock and the feedback clock being unsynchronized; and provide the phase error values to a digital loop filter (DLF) of the DPLL circuit. The TDC circuit further includes clock generation circuitry to: generate a filter clock that asserts a clock pulse in response to detecting each last-received pulse of the input reference clock and the feedback clock; and provide the filter clock to the DLF concurrently with providing the phase error values to the DLF that are synchronized to the filter clock.