DPLL TDC Gain Calibration for Cross-Domain Clock Synchronization
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Solution Overview
Problem
DPLLs in different clock domains of an IC respond differently to jitter in the reference clock due to varying TDC gains, leading to timing issues and communication failures.
Innovation Solution
Implement closed-loop TDC gain calibration circuits to adjust the resolution of TDC circuits in each DPLL to a nominal value, ensuring synchronized clock domains by maintaining a constant control value during calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If DPLLs in different clock domains use different TDC gains to match manufacturing variations, then manufacturing precision is improved, but synchronization reliability deteriorates due to inconsistent jitter responses
Solution Approach 1:
The patent changes the TDC gain parameter dynamically through calibration. Each DPLL includes a calibration circuit that adjusts the TDC gain to a predetermined target value, transforming the fixed manufacturing variation into a calibrated parameter. This allows the system to achieve both manufacturing precision (by accommodating variations) and synchronization reliability (by normalizing the calibrated gain across all DPLLs).
Solution Approach 2:
The patent implements a feedback mechanism where the calibration circuit measures the actual TDC gain and compares it to a target value, then adjusts the gain accordingly. This closed-loop feedback ensures that despite manufacturing variations, all TDCs are calibrated to the same gain value, enabling consistent jitter response across different clock domains while accommodating manufacturing tolerances.
2Measurement precision
If TDC resolution is increased to improve time measurement precision, then measurement precision is improved, but device complexity increases due to additional calibration circuits
Solution Approach 1:
The calibration circuit is integrated within the feedback path of the existing DPLL, allowing the system to self-calibrate without external intervention. The calibration circuit uses the same feedback mechanism already present in the DPLL, measuring the TDC gain and automatically adjusting it to the target value. This self-service approach minimizes additional complexity while achieving high measurement precision.
Solution Approach 2:
The calibration circuit performs multiple functions: it measures the TDC gain, compares it to the target value, and adjusts the gain accordingly. By consolidating these functions into a single integrated circuit within the existing feedback path, the patent avoids the need for separate calibration equipment or complex external calibration systems, thereby reducing overall device complexity while maintaining high measurement precision.
3Productivity
If calibration is performed during DPLL operation, then productivity is improved by avoiding downtime, but measurement precision may temporarily deteriorate during mode switching
Solution Approach 1:
The patent implements periodic calibration where the DPLL operates in normal mode most of the time and switches to calibration mode at predetermined intervals. During calibration mode, the TDC gain is adjusted to the target value, and then the system returns to normal operation. This periodic action ensures that calibration is performed regularly to maintain precision without requiring extended downtime, as each calibration event is brief and the system quickly returns to productive operation.
Solution Approach 2:
The calibration circuit is designed to perform gain adjustment in advance before significant synchronization errors accumulate. By detecting when calibration is needed and performing the adjustment proactively, the system maintains high measurement precision over time. The preliminary calibration action prevents the accumulation of timing errors that would occur if calibration were delayed, thereby minimizing the impact of brief measurement precision deterioration during mode switching.
Data Source
AI summary
In a calibrated digital phase-locked-loop (DPLL) circuit, during a normal operating mode, a control value provided to a digitally controlled oscillator (DCO) is updated by a feedback circuit to keep an output clock generated by the DCO synchronized with a reference clock. The feedback circuit includes a time-to-digital converter (TDC) circuit to measure a phase difference as a time interval. In a calibration operating mode of the calibrated DPLL circuit, calibration of a resolution of a time measurement of the time interval measured by the TDC is performed in the feedback circuit while the control value provided to the DCO is kept constant. Calibrating the TDCs in each of the DPLLs in an integrated circuit (IC) to a nominal resolution in this manner improves synchronization of the clock domains. In some examples, the TDC circuit is a Vernier type circuit and calibration sets a delay difference to a nominal resolution.