Timestamp Correction Using DPLL Phase Measurement for TOD Accuracy
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Solution Overview
Problem
Current methods for achieving accurate time of day (TOD) synchronization in communication networks, such as 5G networks and power networks, face limitations in precision due to clock frequency limitations and the need for complex hardware installations or stringent synchronization requirements.
Innovation Solution
The implementation of a circuit architecture using a single clock tree and digital phase locked loops (DPLLs) to calculate timestamp corrections relative to a reference point, allowing for arbitrary precision in TOD sampling, suitable for FPGA or ASIC implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the frequency of the clock sampling the TOD is increased to improve timestamp precision, then measurement precision improves, but device complexity increases significantly
Solution Approach 1:
The patent introduces an intermediary calculation process using DPLLs that measure the phase difference between the TOD clock and client clocks. Instead of directly sampling at high frequency, the system uses the DPLL to calculate timestamp corrections based on phase measurements, effectively mediating between the TOD clock and client devices to achieve high precision without requiring the TOD clock to run at extremely high frequencies.
2Measurement precision
If multiple phases of the TOD are used to estimate clock position for improved precision, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent replaces complex hardware-based multi-phase sampling systems with a software/mathematical approach using DPLLs. Instead of physically implementing multiple phase detectors and complex hardware circuits, the system uses numerical calculations to determine clock position and phase differences, substituting mechanical/hardware complexity with computational algorithms.
3Measurement precision
If the TOD clock is locked to client frequency to improve precision, then measurement precision improves, but adaptability decreases due to network-wide synchronization requirements
Solution Approach 1:
The patent segments the synchronization problem into independent per-client measurements using individual DPLLs for each client device. Each DPLL operates independently to measure phase differences between the TOD clock and its respective client clock, eliminating the need for network-wide synchronization. This segmentation allows each client to be handled independently, maintaining precision while improving adaptability and reducing configuration constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances timestamp precision by accurately determining the time of day within previous clock intervals, improving synchronization accuracy without the need for complex hardware installations or network-wide synchronization.
Implementation Method 1
a phase detector configured to detect a phase of a clock associated with the TS request
Implementation Method 2
a numerically controlled oscillator ("NCO"), configured to receive the TS request and its phase and calculate a timestamp correction for the TS request relative to the TOD clock
Data Source
AI summary
A method for measuring asynchronous timestamp requests includes receiving a timestamp (“TS”) request from a client device during a first interval of a time of day (“TOD”) clock, and calculating, using the TOD clock, at a next interval of the TOD clock, a TS correction of the TS request relative to a reference point of the first TOD clock interval. The method further includes adding the TS correction to the reference point of the first interval of the TOD clock, and outputting the corrected TS to the client device.