DPLL Timing Normalization Using DTC-Assisted TDC Range Reduction
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Solution Overview
Problem
In All Digital Phase Locked Loops (ADPLLs), achieving a fine resolution while covering multiple cycles of the feedback clock is challenging, especially in Fractional N PLL designs, leading to increased power consumption and design complexity due to the need for a wide range in the Time-to-Digital Converter (TDC).
Innovation Solution
Incorporating a Digital-to-Time Converter (DTC) to predictively delay the reference clock, reducing the range that the TDC needs to cover, and normalizing the output of the TDC to its resolution, eliminating division operations and reducing power consumption by avoiding normalization to the period of the feedback clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the TDC resolution is made finer to achieve low jitter, then the measurement precision is improved, but the device complexity and power consumption increase due to the need for more digital bits and wider range coverage
Solution Approach 1:
The patent segments the time measurement function into two parts: the DTC handles the coarse time range (up to one full cycle of reference clock) by delaying the reference clock edge, while the TDC handles only the fine resolution measurement of the remaining time difference. This segmentation allows the TDC to operate with fewer bits and lower complexity while maintaining overall measurement accuracy.
Solution Approach 2:
The DTC acts as an intermediary between the reference clock and the TDC. It preprocesses the reference clock by introducing a controllable delay based on a digital code, thereby reducing the time range that the TDC must measure. This intermediary function enables the TDC to achieve fine resolution without requiring a wide measurement range, thus reducing complexity and power consumption.
2Adaptability or versatility
If the TDC range is increased to cover multiple cycles of feedback clock in FracN PLL, then the adaptability is improved, but the device complexity and power consumption increase
Solution Approach 1:
The measurement range is segmented between the DTC (handling coarse time offsets up to one reference clock cycle) and the TDC (handling fine time differences). This segmentation allows the system to achieve FracN PLL adaptability without requiring the TDC to cover the full range, thereby reducing power consumption.
Solution Approach 2:
The DTC performs a preliminary action by delaying the reference clock edge before it reaches the TDC. This preliminary delay reduces the time difference that the TDC must measure, enabling the TDC to operate with a smaller range and lower power consumption while still supporting FracN PLL functionality.
3Adaptability or versatility
If the TDC range is increased to cover multiple cycles of feedback clock, then the adaptability is improved, but the device complexity increases
Solution Approach 1:
The patent divides the time measurement task into two segments: the DTC handles the coarse time range (up to one reference clock cycle) by introducing delay, while the TDC handles only the fine resolution measurement. This segmentation enables FracN PLL adaptability without requiring the TDC to have a wide range, thus reducing design complexity.
Solution Approach 2:
The DTC serves as an intermediary that preprocesses the timing signal by introducing a controllable delay. This intermediary function reduces the time range that the TDC must cover, enabling the system to achieve FracN PLL adaptability while keeping the TDC design simple and manageable.
Data Source
AI summary
Embodiments herein describe normalizing an output of a TDC in a DPLL to a resolution of the TDC. A DTC can delay a reference clock which is then input into the TDC. The TDC outputs a digital code indicating a time difference between the delayed reference clock output by the DTC and a clock generated by a DCO in the DPLL. This digital code is normalized to a resolution of the TDC and the result is filtered by a DLF.