Digital Phase-Locked Loop Unwrapping for Wider Lock-In Range
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Solution Overview
Problem
Digital Phase Locked Loops (DPLLs) face issues with false locking states due to limited bandwidth, leading to increased energy consumption and reduced spectral purity, especially when frequency disturbances occur, as they rely on power-hungry components that are difficult to manage efficiently.
Innovation Solution
The implementation of a Digital Phase Locked Loop with an unwrapping unit that processes the Time-to-Digital Converter (TDC) output to increase the capture or lock-in range without increasing loop bandwidth, combined with increasing the out-of-range gain of the TDC, allows for faster relocking and reduced power consumption by deactivating power-hungry integer circuits after initial phase locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the loop bandwidth of the DPLL is increased to prevent false locking states, then the reliability is improved, but the spectral purity deteriorates due to noise increase
Solution Approach 1:
The phase error detection is segmented into two independent circuits: an integer circuit for detecting integer phase errors and a fractional circuit with TDC for detecting fractional phase errors. This segmentation allows each circuit to operate with optimized bandwidth - the integer circuit can use wider bandwidth for fast acquisition and disturbance rejection, while the fractional circuit maintains narrow bandwidth for low noise, resolving the contradiction between reliability and spectral purity.
2Use of energy by moving object
If the integer circuit is switched off to reduce power consumption, then the energy efficiency is improved, but the reliability deteriorates due to false locking states
Solution Approach 1:
The system dynamically switches between integer and fractional circuit operation modes. The integer circuit operates during initial locking and when frequency disturbances are detected, then switches to fractional circuit operation for normal phase locking. This dynamic operation allows power consumption to be reduced while maintaining reliability by activating the integer circuit only when needed for disturbance rejection.
Solution Approach 2:
The system uses feedback from the TDC output to detect when frequency disturbances occur (when output continuously switches between maximum and minimum values). This feedback triggers reactivation of the integer circuit to correct the false locking state, ensuring reliability is maintained while allowing the integer circuit to remain off during normal operation to save power.
3Object-generated harmful factors
If the loop bandwidth is limited to optimize spectral purity, then the spectral purity is improved, but the lock-in range is reduced leading to false locking states
Solution Approach 1:
The phase error detection is segmented into two independent circuits: an integer circuit for detecting integer phase errors and a fractional circuit with TDC for detecting fractional phase errors. This segmentation allows each circuit to operate with optimized bandwidth - the integer circuit can use wider bandwidth for fast acquisition and disturbance rejection, while the fractional circuit maintains narrow bandwidth for low noise, resolving the contradiction between reliability and spectral purity.
Data Source
AI summary
The present disclosure relates to a Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal. The DPLL comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. The DPLL comprises a digitally controlled oscillator for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error. The phase detector comprises an integer circuit for generating a first control signal representative of an integer phase error. The phase detector comprises a fractional circuit comprising a Time-to-Digital Converter (TDC) for processing the feedback signal and a delayed reference clock signal. The fractional circuit is provided for generating from the TDC output a second control signal representative of a fractional phase error. The DPLL comprises an unwrapping unit for unwrapping the TDC output.