Digital Phase-Locked Loop Variable Gain Filter for Fast Lock Time
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Solution Overview
Problem
Conventional digital phase-locked loops experience long lock times when dealing with low-frequency input clock signals, such as those used in GPS or distributed timing applications, which can exceed one hour and degrade further based on input clock signal quality, failing to meet target application specifications of locking time under one minute.
Innovation Solution
The method involves updating the gain of a variable gain digital filter in a digital phase-locked loop using an estimate error of the current phase and frequency of an input clock signal and a measurement error, incorporating both proportional and integral gain components, and updating the gain every cycle of the input clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional digital phase-locked loop with a fixed gain PI controller is used, then the system is simple to implement, but the lock time becomes excessively long (over one hour) for low-frequency input clock signals
Solution Approach 1:
The patent implements a variable gain digital filter where the gain is dynamically adjusted based on the current estimation error and measurement error. The gain updates every cycle of the input clock signal, transitioning from a static fixed-gain system to a dynamic adaptive system that optimizes performance for low-frequency signals while maintaining stability.
Solution Approach 2:
The patent introduces a feedback mechanism where the gain of the digital filter is continuously updated based on the comparison between the current estimate of phase and frequency and the actual measurements. This feedback loop enables the system to adapt to varying signal conditions and achieve faster lock times.
2Loss of time
If the loop bandwidth is increased to reduce lock time, then the locking speed improves, but the stability and noise rejection deteriorate
Solution Approach 1:
The variable gain digital filter dynamically adjusts the loop bandwidth by updating the gain based on estimation and measurement errors. This allows the system to effectively widen the bandwidth during acquisition to reduce lock time, then narrow it during tracking to maintain stability and noise rejection, resolving the trade-off between speed and reliability.
3Adaptability or versatility
If a fixed gain digital filter is used, then the system is easier to implement, but it cannot adapt to varying input clock signal qualities and frequencies
Solution Approach 1:
The patent implements feedback-based gain adaptation where the digital filter's gain is continuously adjusted based on the difference between estimated and measured phase and frequency values. This feedback mechanism enables the system to adapt to varying input signal qualities and frequencies while maintaining a relatively simple implementation structure.
Solution Approach 2:
The patent changes the gain parameter of the digital filter dynamically based on the estimation error and measurement error. This parameter adaptation allows the system to optimize its performance for different input signal conditions without requiring a complete redesign of the filter structure.
Data Source
AI summary
A method for generating a clock signal using a digital phase-locked loop includes updating a gain of a variable gain digital filter of the digital phase-locked loop using an estimate error of a current estimate of a phase and a frequency of an input clock signal and a measurement error of a measurement of the phase and the frequency of the input clock signal. The gain may include a proportional gain component and an integral gain component. The method may include calculating the current estimate of the phase and the frequency of the input clock signal based on a previous estimate of the phase and the frequency of the input clock signal, the measurement of the phase and the frequency of the input clock signal, and the gain of the variable gain digital filter. The gain may be updated every cycle of the input clock signal.