DPSK Receiver Module Iterative Decoding for Signal Attenuation

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Solution Overview

Problem

Conventional digital audio broadcast (DAB) systems face challenges in maintaining adequate bit error rates (BERs) when received signal strength is attenuated, due to limitations in differential quadrature phase shift keying (D-QPSK) modulation.

Innovation Solution

A receiver module is implemented with symbol-level de-interleaving, iterative decoding, and forward error correction techniques, including a turbo code loop that reduces memory requirements and decoding latency, enhancing sensitivity by several decibels compared to state-of-the-art receivers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional D-QPSK modulation is used in DAB systems, then the system can maintain basic functionality, but the bit error rate performance deteriorates when received signal strength is attenuated

Engineering Contradiction:
Improvebit error rate performanceVSAvoidsignal attenuation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The receiver performs symbol-level de-interleaving before demodulation to redistribute symbols and exploit diversity. This preliminary processing prepares the signal for improved error correction in subsequent decoding stages, enhancing performance before the harmful effect of attenuation fully impacts the demodulation process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements iterative decoding with a turbo code loop where the forward error correction decoder provides feedback to the symbol demodulator. This feedback mechanism allows the receiver to progressively refine its estimation of transmitted symbols, improving bit error rate performance by several decibels compared to non-iterative approaches.

Inventive Principle:
Principle #23Feedback

2Reliability

If iterative decoding with turbo code loop is implemented, then sensitivity is improved by several decibels, but memory requirements and decoding latency increase

Engineering Contradiction:
Improvereceiver sensitivityVSAvoidmemory requirements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The iterative decoding process is segmented into discrete stages: symbol de-interleaving, demodulation, forward error correction decoding, and re-encoding. Each stage processes a specific portion of the signal and passes results to the next stage, allowing the system to achieve improved sensitivity through multiple iterations while managing memory requirements through structured data flow between segmented processing blocks.

Inventive Principle:
Principle #1Segmentation

3Reliability

If symbol-level de-interleving is performed, then diversity is exploited and burst errors are suppressed, but processing complexity increases

Engineering Contradiction:
Improveerror suppression capabilityVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The symbol de-interleaver acts as an intermediary component between the received signal and the demodulator. It redistributes symbols to exploit diversity and suppress burst errors before the signal enters the demodulation stage, thereby improving reliability without requiring the demodulator itself to handle the complexity of burst error correction.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3361659B1Dpsk receiver module
Publication Date: 2020.01.08 NXP BV
  • EP3361659B1 patent drawingFigure 1
  • EP3361659B1 patent drawingFigure 2
  • EP3361659B1 patent drawingFigure 2

AI summary

The disclosure relates to a receiver module for determine error-corrected bits from differential phase shift keyed, D-PSK, symbols, the receiver module comprising: a symbol de-interleaver configured to receive the D-PSK symbols and perform symbol-level deinterleaving to generate de-interleaved D-PSK symbols; a symbol demodulator configured to generate demodulated bits based on the de-interleaved D-PSK symbols generated by the symbol de-interleaver; a forward error correction decoder configured to provide error-corrected bits based on the demodulated bits; and a forward error correction encoder configured to encode the error-corrected bits and to provide the encoded bits to the symbol demodulator, wherein the symbol demodulator is further configured to regenerate the demodulated bits based on the encoded bits.