DPT Interconnect Routing via Two-Color Graph Coloring
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Solution Overview
Problem
Double patterning technology (DPT) in integrated circuits faces challenges in achieving desired tradeoffs between fabrication costs and yield, particularly due to computationally intensive methods required to resolve color conflicts and ensure DPT compatibility, which often result in larger pattern areas and increased costs.
Innovation Solution
A reduced set of DPT compatible design rules and color cover methodologies are introduced to simplify the process of generating DPT compatible interconnect patterns, allowing for manual or automated layout without extensive computation, using EDA tools like IC COMPILER and VIRTUOSO, and employing color covers to reduce pattern area by altering geometry colors and applying specific design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If unrestricted routing layout is used, then layout flexibility is improved, but color conflicts occur which violate DPT design rules
Solution Approach 1:
The patent applies preliminary action by performing graph coloring on the routing layout before final pattern generation. The routing graph is constructed and colored using only two colors (first and second colors) to pre-assign geometries to different photo masks, ensuring DPT compliance is achieved beforehand rather than corrected afterward. This preliminary coloring step prevents color conflicts before they violate design rules.
Solution Approach 2:
The patent changes the parameter of geometry color assignment from unrestricted to constrained, using only two colors (first and second colors) for all geometries. This parameter change transforms the layout from potentially conflict-prone unrestricted coloring to DPT-compliant two-color assignment, where adjacent geometries automatically have different colors, eliminating color conflicts while maintaining layout flexibility.
2Reliability
If computationally intensive DPT compatibility methods are used, then DPT compliance is improved, but pattern area increases and cost increases
Solution Approach 1:
The patent changes the parameter of design rule application by using a reduced set of DPT compatible design rules that are specifically tailored for two-color routing. Instead of applying all possible DPT constraints, the patent uses optimized rules (such as Rule 1: geometries of the first color must be separated by at least the same-color minimum pitch; Rule 2: geometries of the second color must be separated by at least the same-color minimum pitch) that achieve DPT compliance with minimal spacing requirements, thereby reducing pattern area.
Solution Approach 2:
The patent uses graph coloring theory to create a simplified representation (copy) of the routing layout where nodes represent geometries and edges represent adjacencies. This graph copy is then colored using two colors to determine mask assignment, avoiding the need to process all geometric details simultaneously and reducing computational intensity while maintaining DPT compliance.
3Reliability
If computationally intensive relayout methods are used, then DPT compliance is improved, but fabrication cost increases
Solution Approach 1:
The patent performs graph coloring and mask assignment as a preliminary action during the routing phase rather than as a post-processing relayout step. By constructing the routing graph and assigning colors (first or second mask) to each geometry during layout generation, the system ensures DPT compliance is built-in from the start, eliminating the need for expensive and time-consuming relayout operations later in the fabrication process.
Solution Approach 2:
The patent changes the parameter of routing approach from conventional single-color routing to two-color routing with specific design rules. This parameter change enables DPT compliance to be achieved during the routing process itself using simplified rules (such as alternating colors for adjacent geometries and minimum pitch separations), avoiding the need for complex and costly relayout operations that would be required if DPT compliance were enforced afterward.
Data Source
AI summary
A method of generating an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and color covers. A method of operating a computer to generate an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and using color covers. A reduced DPT compatible design rule set.