DPT Odd Loop Visualization for IC Layouts
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Solution Overview
Problem
In integrated circuit design, particularly at lower geometric nodes, the detection and visualization of odd loops in Double Patterning Technology (DPT) processes are challenging due to complexity and the difficulty in assigning appropriate masks, leading to manufacturability issues.
Innovation Solution
A computer-implemented method and system that maps design layout violations to a graph, partitions the graph into sub-graphs, detects odd loops, and visualizes them to facilitate identification and correction of odd loops, allowing designers to easily understand and fix these violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If DPT is used to print images at 20 nm or below technology, then manufacturing precision is improved, but device complexity increases due to associated rules and odd loop detection challenges
Solution Approach 1:
The patent segments the complex DPT violation detection process into distinct modules: graph generation from layout data, odd loop detection algorithms, and visualization components. This segmentation allows each module to handle specific aspects of the problem independently, reducing overall system complexity while maintaining manufacturing precision at 20 nm and below
Solution Approach 2:
The patent introduces an intermediary graph representation that translates complex layout geometry into a simplified network structure. This intermediary model enables efficient odd loop detection without directly processing the full complexity of the original layout, thus resolving the contradiction between precision and complexity
2Manufacturing precision
If comprehensive odd loop detection is implemented in DPT, then manufacturing precision is improved, but loss of time increases due to the computational complexity of detecting and visualizing all odd loops
Solution Approach 1:
The patent performs preliminary actions by pre-processing the layout data into a graph structure before odd loop detection. This preliminary transformation organizes the data in a way that accelerates subsequent detection operations, reducing the time penalty while maintaining comprehensive detection capability
Solution Approach 2:
The patent creates a copied representation of the layout as a graph structure, which is then used for odd loop detection. This copying approach allows the original layout to remain unchanged while enabling efficient detection operations on the replicated graph model, balancing comprehensiveness with speed
Data Source
AI summary
Computer-implemented method, system and computer program product for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout are disclosed. The method, system and computer program product comprise mapping all violations of the integrated circuit design layout to a graph. The method, system and computer programming product also includes partitioning the graph into a plurality of sub-graphs. Each of the plurality of sub-graphs includes multiple edges and multiple nodes. The method, system and computer product further include detecting all possible odd loops in each of the plurality of sub-graphs; and visualizing all of the odd loops in at least one of the plurality of sub-graphs.