DPT Compatible Via Design Rules for IC Autorouting
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Solution Overview
Problem
Double patterning technology (DPT) for integrated circuits faces challenges in achieving tight pitch alignment without excessive alignment errors, leading to increased fabrication costs and yield loss, particularly in via patterns that require multiple photomasks and are prone to misalignment, which affects contact area and resistance.
Innovation Solution
A reduced DPT compatible via design rule set is implemented, allowing for autorouting of via patterns using EDA tools without excessive computation, ensuring alignment and reducing pattern area, by defining vias on a fixed grid formed by underlying and overlying interconnect patterns, with specific rules for via shape, pitch, and width to ensure self-alignment and minimize misalignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple DPT photomasks are used to print tight pitch via patterns in both x and y directions, then the pitch requirement is met, but the number of alignment errors increases significantly
Solution Approach 1:
The via pattern is segmented into two sets of alternating rows (odd and even rows) that can be printed separately using two DPT photomasks. This segmentation allows each mask to cover only specific rows, reducing the cumulative alignment errors compared to using four masks for all directions.
Solution Approach 2:
The patent applies asymmetric design rules where via rows in different directions (x and y) are treated differently. By assigning alternating rows to different masks and using asymmetric pitch relationships (e.g., via pitch in one direction being twice the interconnect pitch), the design reduces the number of masks needed while maintaining tight pitch requirements.
2Ease of manufacture
If standard single photoresist patterns are used, then fabrication cost is reduced, but pattern blur occurs at 45 nm feature size and 100 nm pitch
Solution Approach 1:
The patent employs periodic action through double patterning technology, where patterns are formed in two sequential steps using two photomasks. Each mask prints alternating rows of features, and the combined result achieves the desired tight pitch pattern that cannot be obtained with a single exposure, thereby preventing pattern blur at 100 nm pitch.
3Manufacturing precision
If via patterns are aligned separately for each photomask, then tight pitch in both directions can be achieved, but yield loss increases due to multiple alignment errors
Solution Approach 1:
The patent merges the printing of via patterns by using only two DPT photomasks instead of four, combining the functionality of multiple masks into fewer masks. This merging reduces the number of alignment operations from four to two, thereby reducing cumulative alignment errors and improving yield while still achieving tight pitch in both x and y directions.
Data Source
AI summary
A method of generating an integrated circuit with a double patterning technology (DPT) compatible via pattern using a reduced DPT compatible via design rule set. A reduced DPT compatible via design rule set. A method of forming an integrated circuit using a via pattern generated from a reduced DPT compatible design rule set.