DPU Hardware Accelerators for Data Stream Processing

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Solution Overview

Problem

Current data analytics platforms face inefficiencies in processing large volumes of data due to reliance on general-purpose processors for query predicate execution, leading to slow analytics operations and high computational overhead.

Innovation Solution

The implementation of data flow graph-driven analytics platforms utilizing highly programmable data processing units (DPUs) with hardware-based accelerators, such as regular expression engines, to efficiently process and analyze data streams by transforming queries into DFA and NFA representations and applying them directly to data flows, reducing the need for general-purpose processor involvement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If general-purpose processors are used for query predicate execution, then device versatility is maintained, but processing speed and computational efficiency deteriorate

Engineering Contradiction:
Improveprocessing speedVSAvoidprocessor versatility
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The system segments processing tasks by separating general-purpose query execution from specialized predicate evaluation. General-purpose processors handle high-level query orchestration while specialized hardware accelerators handle specific predicate operations (regex matching, filtering, aggregation), resolving the contradiction by dividing work between versatile and specialized components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces data flow graphs as an intermediary layer between general-purpose processors and specialized hardware accelerators. The data flow graph compiler translates queries into optimized execution plans that leverage specialized hardware, allowing general-purpose processors to maintain versatility while specialized hardware provides acceleration without direct coupling.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If hardware-based accelerators are deployed for data stream processing, then processing efficiency improves, but device complexity increases

Engineering Contradiction:
Improvedata processing throughputVSAvoidsystem architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements universal data flow graph nodes that can represent multiple types of operations (filtering, aggregation, joining, regex matching) within a unified framework. This allows diverse data processing tasks to be handled by the same hardware infrastructure, increasing productivity while managing complexity through abstraction.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system uses data flow graphs as virtual representations of processing pipelines that can be compiled and deployed to various hardware configurations. This virtualization layer allows complex hardware architectures to be managed through simpler software abstractions, enabling high throughput while managing device complexity through modeling rather than direct hardware management.

Inventive Principle:
Principle #26Copying

3Speed

If specialized data processing units are used for analytics operations, then processing speed improves, but computational resource requirements increase

Engineering Contradiction:
Improveanalytics processing speedVSAvoidcomputational resources
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent applies local quality by deploying specialized processing capabilities only where needed in the data flow graph. Rather than requiring all nodes to have full analytical capabilities, only specific nodes performing predicate evaluation or pattern matching utilize specialized hardware, reducing overall computational resource requirements while maintaining high processing speed for critical operations.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11263190B2Data ingestion and storage by data processing unit having stream-processing hardware accelerators
Publication Date: 2022.03.01 MICROSOFT TECHNOLOGY LICENSING LLC
  • US11263190B2 patent drawing
  • US11263190B2 patent drawing
  • US11263190B2 patent drawing

AI summary

A system comprises a data processing unit (DPU) integrated circuit having programmable processor cores and hardware-based accelerators configured for processing streams of data units; and software executing on one or more of the processing cores. In response to a request to perform an operation on a set of one or more data tables, each having one or more columns of data arranged in a plurality of rows, the software configures the DPU to: input at least a portion of the rows of each of the database tables as at least one or more streams of data units, process the one or more streams of data units with the hardware-based accelerators to apply one or more of compression, encoding or encryption to produce a resultant stream of data units; and write the resultant stream of data units to a storage in a tree data structure.