DRAM Processing Unit for Deep Learning via In-Memory Logic

The system segments the computing task across multiple independent DRAM-based computing cells arranged in arrays, where each cell can perform parallel operations. This segmentation enables highly parallelized processing by distributing computations across numerous simple, identical units that operate simultaneously on different data elements.

The patent replaces conventional von Neumann architecture with in-memory computing using DRAM cells that perform logic operations directly during read/write cycles. This eliminates the mechanical bottleneck of data transfer between CPU and specialized units, substituting it with parallel in-memory operations that achieve higher throughput for parallelized deep learning tasks.

The DRAM-based computing cells are designed to be universal, capable of performing multiple logic functions (AND, OR, NOT, NOR) depending on the control signals applied during read/write operations. This multi-functionality reduces device complexity by eliminating the need for separate dedicated logic circuits for each operation, while maintaining high parallel processing capability through the array structure.

The system changes the operational parameters of DRAM cells by applying different control signals (read enable, write enable, mask signals) to transform simple memory cells into functional logic units. This parameter-based configuration allows the same physical hardware to perform diverse computing functions without adding structural complexity, enabling parallel processing through software-controlled cell activation patterns.