DPU Packet Offload Using Exact-Match Tables for Low-Latency Routing
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Solution Overview
Problem
Traditional packet processing systems face inefficiencies due to the use of vendor-specific ASICs with TCAMs requiring reordering of routes, leading to increased latency and reduced throughput, especially in handling large volumes of data packets.
Innovation Solution
Implementing a DPU-based offload architecture that utilizes CAMs with exact match flow entries, combining a hardware switch pipeline with a software data plane to minimize latency and enhance throughput by eliminating the need for reordering routes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If vendor-specific ASICs with TCAMs are used for packet processing, then hardware acceleration is achieved, but route reordering is required causing increased latency and reduced throughput
Solution Approach 1:
The patent changes the data structure parameter from traditional TCAM to CAM (Content Addressable Memory), and changes the routing entry format from full routes to prefix routes. This parameter change eliminates the need for route reordering while maintaining hardware acceleration capabilities, thereby reducing processing latency and increasing throughput.
Solution Approach 2:
The patent segments the routing table into prefix routes stored in CAM and exact match flow entries stored in separate hardware tables. This segmentation allows the CAM to handle prefix matching without requiring reordering of all routes, thus reducing the processing burden and latency associated with traditional TCAM route reordering.
2Adaptability or versatility
If traditional CPU-based packet processing is used, then flexibility is maintained, but processing load increases significantly reducing system performance
Solution Approach 1:
The patent extracts packet processing functionality from the CPU and implements it in a dedicated hardware switch pipeline with CAM-based routing. This extraction reduces the CPU processing load by 20-40% while maintaining the flexibility needed for network packet processing through the hardware acceleration layer.
Solution Approach 2:
The patent introduces a hardware switch pipeline as an intermediary between the CPU and the network interface. This intermediary handles packet processing operations that would otherwise burden the CPU, thereby maintaining system flexibility while significantly improving processing capacity.
3Speed
If routes are programmed into TCAM for hardware processing, then packet forwarding is accelerated, but route reordering operations increase processing complexity and time
Solution Approach 1:
The patent changes the routing entry parameter from full routes requiring reordering to prefix routes that do not require reordering. This parameter change simplifies the route programming operation while maintaining hardware acceleration, thereby reducing processing complexity and time.
Solution Approach 2:
The patent performs preliminary action by storing prefix routes in CAM before packet processing occurs. This preliminary storage of prefix information in the CAM allows for fast lookup during packet processing without requiring reordering operations, thus simplifying the overall route programming complexity.
Data Source
AI summary
A method for processing packets, comprising receiving a packet via a representor port on a data processing unit (DPU) operatively connected to a physical host, in response to receiving the packet, processing packet using a hardware switch pipeline in the DPU, where the processing the packet comprises using a plurality of match/action tables to identify an exact match flow entry for the packet, where the plurality of match/action tables do not contain any match flow entries that are not exact match flow entries; and initiating transmission of the packet towards its intended destination using the exact match flow entry.